Synthesis of assertions from statements of power intent

Details Synthesis of assertions from statements of power intent Synthesis of assertions from statements of power intent

2011-06-07

2011-06-07

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

Reexamination Certificate

active

07958475

ABSTRACT:
A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low power functional coverage data.

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Balarin et al., “Constraints Specification at Higher Levels of Abstraction,” Proceedings of Sixth IEEE Int'l High-Level Design Validation and Test Workshop, Nov. 7-9, 2001, pp. 129-133.

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