Syncronous dynamic semiconductor memory device using pipelined m

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36523006, 36518905, 365236, G11C 800

Patent

active

057038309

ABSTRACT:
In a synchronous dynamic semiconductor memory device, a plurality of data paths, each of which is formed by a column decoder, a sense amplifier and a first-stage data amplifier, are provided between a column address buffer having a burst counter function and a second-stage data amplifier which is further connected to a data latch circuit.

REFERENCES:
patent: 5384737 (1995-01-01), Childs et al.
patent: 5610874 (1997-03-01), Park et al.
patent: 5633834 (1997-05-01), Pascucci

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