Synchronous up/down address generator for burst mode read

Details Synchronous up/down address generator for burst mode read Synchronous up/down address generator for burst mode read

2005-04-26

2005-04-26

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230080, C365S233100

Reexamination Certificate

active

06885589

ABSTRACT:
A symmetrical divide-by-2 circuit has a master latch made up of two inverters. The circuit has an inverter on each output. The capacitance of these inverters forms a dynamic slave latch that is connected to the master latch through a transmission gate on each master latch output. The data is transferred from the master latch to the dynamic slave latch every clock cycle by an enable clock and an inverse of the enable clock. Capacitance leakage is reduced by the transmission gates until the next clock cycle. The circuit is clocked by a one-shot clock that is self-aligning to the latest transition of either the enable clock or inverse enable clock.

REFERENCES:
patent: 5208480 (1993-05-01), Ishibashi
patent: 5621338 (1997-04-01), Liu et al.
patent: 5822252 (1998-10-01), Lee et al.
patent: 5862099 (1999-01-01), Gannage
patent: 6163500 (2000-12-01), Wilford

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