Synchronous type semiconductor memory system with less power...

Details Synchronous type semiconductor memory system with less power... Synchronous type semiconductor memory system with less power...

2000-06-26

2001-05-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S227000, C365S189050

Reexamination Certificate

active

06240048

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a power saving function.
2. Description of the Related Art
Very recently, synchronous DRAMs (Dynamic Random Access Memories) capable of achieving high-speed access operations and high data bandwidths have been marketed in 16-Mbit generation and further 64-Mbit generation. In such a synchronous DRAM, all of memory operations thereof are performed in synchronous with a external clock signal CLK. Also, the synchronous DRAM is typically provided with a power down mode to reduce current consumption of an input buffer.
FIG. 1
is a diagram showing the structure of a conventional synchronous DRAM with such a power down mode. Referring to
FIG. 1
, in this conventional synchronous DRAM circuit, a clock signal CLK is supplied to an input buffer circuit
51
b,
a chip select signal CSB is supplied to another input buffer circuit
51
c,
and a row address strobe signal RASB is supplied to another input buffer circuit
51
d.
Also, a column address strobe signal CASB is supplied to another input buffer circuit
51
e,
and a write enable signal WEB is supplied to a further input buffer circuit
51
f.
Address signals A
0
to A
11
are supplied to the input buffer circuit
51
h,
and data signals DQ
0
to DQ
15
are supplied to the input buffer circuit
51
i.
A combination of three types of signals such as the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB gives one of various types of commands. For example, a data write command CMD and a data read command (CMD) may be applied to an SDRAM. The address signals A
0
to A
11
are applied in combination with commands CMDs, so that addresses of memory cells are designated. Furthermore, a mask signal U/LDQM is supplied to the input buffer circuit
51
g.
This mask signal U/LDQM causes the data D
0
to D
15
not to be read out from the SDRAM, or causes the data D
0
to D
15
not to be written into the SDRAM.
On the other hand, a clock enable signal CKE is supplied via another input buffer circuit
51
a
to a power down control circuit
52
. In response to the clock enable signal CKE, the power down control circuit
52
generates power down signals PWDNB and PWDNBQ. The power down signal PWDNB is supplied to these input buffer circuits
51
b,
51
c,
51
d,
51
e,
51
f,
51
g
and
51
h,
whereas the power down signal PWDNBQ is supplied to another input buffer circuit
51
i.
As shown in
FIG. 4
, each of the input buffer circuits
51
b
to
51
h
of each of the SDRAMs is composed of a current mirror type pre-stage circuit
71
and a buffering circuit
72
. When the power down signal PWDNB is in a high level, the current mirror type pre-stage circuit
71
is set to an active state. Conversely, when the power down signal PWDNB is in a low level, the current mirror type pre-stage circuit
71
is set to a power down state. The current mirror type pre-stage circuit
71
operating in the active state continuously consumes a current passing from a power supply potential Vcc to the ground potential GND through P-channel type transistors
71
a,
71
b,
and
71
c
and N-channel type transistors
71
d,
71
e,
and
71
f.
The passing-through current will be referred to as a “DC current” hereinafter. Symbol “Vref” indicates a reference signal used to determine whether a level of a command CMD is in a low level or a high level. The level of the reference signal Vref is in an intermediate level between the power supply potential Vcc and the groudn potential GND. The buffering circuit
72
is provided to transfer a command CMD with a high level or a low level to an internal circuit of the SDRAM. The buffering circuit
72
operates only when the current mirror type pre-stage circuit
71
is set to the active state, and consumes a current when the level of the command CMD is switched from the high level to the low level, or vice versa. The current consumed by the buffering circuit
72
at that time will be referred to as an “AC current” hereinafter.
Now, a current consumption condition in the conventional synchronous type semiconductor memory system will be described below. As shown in
FIG. 1
, each of these SDRAMs determines whether the power down signal PWDNB supplied from the power down control circuit
52
is in the high level or the low level, depending on the input state of the clock enable signal CKE. That is, when the clock enable signal CKE is in the high level, the power down signal PWDNB becomes the high level, so that the input buffer circuit operate. Conversely, when the clock enable signal CKE is in the low level, the power down signal PWDNB becomes the low level, so that the input buffer circuit does not operate. The data signals DQ
0
to DQ
15
shown in
FIG. 1
are supplied with the power down signal PWDNBQ which is a inversion signal of the power down signal PWDNB. Even if the clock enable signal CKE is in the high level, the power down signal PWDNBQ becomes the low level. Therefore, when a reading command CMD is supplied, the data signals DQ
0
to DQ
15
can be accessed.
FIG. 2
shows an example of an arrangement of a memory system in which n SDRAMs each having the structure shown in
FIG. 1
are mounted. As shown in
FIG. 2
, a plurality of SDRAMs
61
to
6
n are provided in a memory system. A chip select signal CSB is supplied to specify one of the SDRAMs for a command CMD to be applied. It should be noted that an address signal A, a mask signal U/LDQMB, a data signal DQ, a command CMD, a clock CLK, and a clock enable signal CKE are commonly used to the n SDRAMs
61
to
6
n. As an exceptional case, the respective SRAMs has the specific signal lines for the chip select signals CSB. Thus, the respective chip select signals CSB
1
to CSBn are supplied to the respective SDRAMs
61
to
6
n.
FIGS. 3A
to
3
G are timing charts showing an example of operations of the SDRAM memory system. When the level of the clock signal CKE becomes high as shown in
FIG. 3A
, the power down signals PWDNB
1
to PWDNBn for synchronous type memories
61
to
6
n become high as shown in FIG.
3
C. In case that a command CMD of “ACT-1” shown in
FIG. 3G
is applied to the synchronous type memory
61
, the chip select signal CSB
1
is set to a low level. When the clock signal CLK for the chip select signal CSB
1
is in the high level, the command CMD of “ACT-1” is applied to the SDRAM
61
only while the chip select signal CSB becomes a low level. Similarly, when a command of “ACT-2” shown in
FIG. 3E
is applied to the synchronous type memory
62
, the chip select signal CSB
2
becomes low. Other synchronous type memories are controlled in a similar manner. At that time, the synchronous type memories
61
to
6
n continuously consume a DC current while the clock enable signal CKE is in the high level, and also the power down signals PWDNB
1
to PWDNBn become high. Also, when the command CMD is switched between the high level and the low level, an AC current is consumed in the synchronous type memories
61
to
6
n, irrespective of the DC current.
In this way, in the conventional SDRAM system, although a command is applied to one of SDRMs of the memory system, other SDRAMs also consume currents.
In conjunction with the above description, a power cutting circuit for a synchronous semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-177015). In this reference, a power cutting circuit (
11
,
12
,
13
and
14
) cuts the power supplied to an input initial stage circuit connected to external input/output pin in a standby state or in a reading operation. Also, when an input is supplied to another input pin to make the output of the external input/output pin invalid, the power cutting circuit powers on the input initial stage circuit. Thus, consumption current is reduced by cutting the power supplied to the input initial stage circuit in a mode other than a power down mode in a synchronous-type DRAM.
Also, a power down memory control unit is disclosed in Japanese Lai

Affiliated with

Also associated with

Rating

Synchronous type semiconductor memory system with less power... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous type semiconductor memory system with less power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous type semiconductor memory system with less power... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2512844