Synchronous type semiconductor integrated circuit having a...

Details Synchronous type semiconductor integrated circuit having a... Synchronous type semiconductor integrated circuit having a...

2000-03-16

2001-11-06

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C375S375000

Reexamination Certificate

active

06313676

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the Japanese Patent Application No. 11-069912, filed Mar. 16, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a synchronous semiconductor integrated circuit which generates an internal clock signal synchronizing with an external clock signal and performs input/output control of data in synchronization with the internal clock signal, and more particularly to a synchronous semiconductor integrated circuit used in, for example, a synchronous DRAM or a RAMBUS DRAM which generates an internal clock according to the load characteristic of an external data bus onto which data is outputted.
As the operating speed of a semiconductor integrated circuit is made higher, this gives rise to a problem: even a slight delay between the internal clock signal driving the internal circuit and the external clock signal causes the circuit to operate erroneously.
Such a problem can be solved by incorporating a clocked delay control circuit into a semiconductor integrated circuit.
The clocked delay control circuit synchronizes with an external clock signal and generates a delay signal delayed for n (n is an integer) periods of the external clock signal. This signal is used as an internal clock signal.
Hereinafter, the clocked delay control circuit will be explained briefly.
Clocked delay control circuits are available in two types: those of the SAD type using a synchronous adjustable delay (hereinafter, referred to as SAD) and those of the DLL type using a delay locked loop (hereinafter, referred to as DLL). Clocked delay control circuits of both types use delay lines to synchronize the internal clock signal with the external clock signal.
The SAD type of clocked delay control circuit generates a signal caused to lag behind the external clock signal by an integral multiple of the period without using a feedback loop and uses this signal as an internal clock signal. The PLL type of clocked delay control circuit compares the phase of the internal clock signal with that of the external clock signal using a feedback loop and controls the delay lines according to the phase difference, thereby generating an internal clock signal synchronizing with the external clock.
FIG. 1
is a block diagram of a conventional clocked delay control circuit of the SAD type. The clocked delay control circuit includes of a clock receiver
11
to which an external clock signal ExtCLK is inputted, a delay monitor
12
for delaying the output of the clock receiver
11
, a forward pulse delay line
14
which is composed of unit delay circuits
13
and delays the output signal FCL of the delay monitor
12
by causing the unit delay circuits
13
to propagate the output signal FCL as a forward pulse in sequence, a control circuit
15
to which the output signal CLK of the clock receiver
11
is supplied, a backward pulse delay line
16
which is composed of unit delay circuits
13
and delays the backward pulse transferred from the forward pulse delay line
14
by causing the unit delay circuits
13
to propagate the backward pulse sequentially, and an output buffer
17
to which the output signal RCL from the backward pulse delay line
16
is inputted and outputs an internal clock signal IntCLK.
The operating principle of the clocked delay control circuit will be explained by reference to timing charts in
FIGS. 2A
to
2
E.
As shown in
FIGS. 2A
to
2
E, the external clock signal ExtCLK with a period of T is amplified and waveform-shaped by the clock receiver
11
and becomes a signal CLK delayed for a delay time of tRC in the clock receiver
11
. The signal CLK is inputted to the control circuit
15
and simultaneously to the delay monitor
12
. The delay monitor
12
has a delay time of tDM (tDM=tRC+tDR) equal to the sum of the delay time tRC in the clock receiver
11
and the delay time tDR in the output buffer
17
. The signal delayed by the delay monitor
12
is inputted as a signal FCL to the forward pulse delay line
14
.
The control circuit
15
has the function of, when the signal CLK is at the high level, stopping the propagation of the forward pulse on the forward pulse delay line
14
and transferring the signal to the backward pulse delay line
16
. Thus, the signal FCL is propagated and delayed as a forward pulse over the forward pulse delay line
14
during a period of (T−tDM) until the signal CLK has risen. Thereafter, the signal FCL is transferred to the backward pulse delay line
16
(this time is represented by t in
FIGS. 2A
to
2
E).
The signal transferred to the backward pulse delay line
16
is propagated and delayed as a backward pulse over as many unit delay circuits
13
in the backward pulse delay line
16
as the forward pulse has in the forward pulse delay line
14
. Then, the backward pulse delay line
16
outputs the signal as a signal RCL delayed a period of (T−tDM) from time t. The signal RCL is further delayed for the delay time tDR at the output buffer
17
and outputted as an internal clock signal IntCLK.
A delay time of &Dgr;TOTAL on the internal clock signal IntCLK with respect to the external clock signal ExtCLK is given as follows:
&Dgr;TOTAL=
tRC+tDM+
2(
T−tDM
)+
tDR
  (1)
Since tRC+tDR=tDM, equation (1) is simplified as follows:
Δ
⁢
 
⁢
TOTAL
=
(
tRC
+
rDR
)
+
tDM
+
2
⁢
T
-
2
⁢
tDM
=
tDM
+
tDM
+
2
⁢
T
-
2
⁢
tDM
=
2
⁢
T
(
2
)
Thus, the internal clock signal starts to synchronize with the external clock signal at the third period of the external clock signal.
FIG. 3
is a block diagram of a conventional clocked delay control circuit of the DLL type.
The DLL clocked delay control circuit includes a clock receiver
11
, a delay line
14
A, an output buffer
17
, a control circuit
15
A composed of a shift register, a delay monitor
12
A, and a phase comparator
18
.
The operating principle of the DLL clocked delay control circuit will be explained by reference to timing charts in
FIGS. 4A
to
4
E.
As shown in
FIGS. 4A
to
4
E, the external clock signal ExtCLK with a period of T is amplified and waveform-shaped by the clock receiver
11
. The resulting signal is then outputted as a signal CLKA delayed for the delay time tRC in the clock receiver
11
. The signal CLKA is inputted to the delay line
14
A and phase comparator
18
.
As shown in
FIG. 3
, the delay line
14
A is composed of n unit delay circuits
13
connected in a multistage manner. The signal CLKA is inputted to the unit delay circuit
13
k at the k-th stage (1≦k≦n). Then, the unit delay circuit
13
n at the n-th stage, the last stage, outputs the signal as a signal CLKAd.
The signal CLKAd is inputted to the delay monitor
12
A. The delay monitor
12
A has a delay time of tDM (tDM=tRC+tDR) equal to the sum of the delay time tRC in the clock receiver
11
and the delay time tDR in the output buffer
17
. The signal delayed by the delay monitor
12
A is inputted as a signal CLKB to the phase comparator
18
, which compares the phase of the signal CLKB with that of the previous signal CLKA. The result of the comparison is inputted to the control circuit
15
A. According to the result of the comparison, the control circuit
15
A changes the position of the stage of the unit delay circuit
13
to which the signal CLKA is inputted.
The signal CLKAd is further delayed by the output buffer
17
for its delay time tDR. The delayed signal is outputted as an internal clock signal IntCLK.
If the delay time occurring on the delay line
14
A with respect to the signal CLKA is t(k), a delay time of &Dgr;TOTAL on the internal clock signal IntCLK with respect to the external clock signal ExtCLK is given by the following equation:
&Dgr;TOTAL=
tRC+t
(
k
)+
tDR
  (3)
The phase difference &Dgr;AB between signal CLKA and signal CLKB is:
&Dgr;
AB=t
(
k
)+
tDM
  (4)
When k is so determine

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