Synchronous-type memory

Static information storage and retrieval – Addressing – Sync/clocking

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36523006, G11C 700

Patent

active

057401217

ABSTRACT:
A synchronous-type memory performing in synchronization with a clock provided from an external device. This memory includes memory cells for storing data and selected by one of word lines, a decoder and a S/A. The decoder latches an address to select a word line in accordance with a rising edge of the clock, selecting a word line, and deselecting all word lines in accordance with a falling edge of the clock. The S/A stores the data transferred from the memory cell belonged to the word line selected by the decoder in synchronism with the rising edge of the clock before all the word lines is switched by the decoder to a deselected state, synchronized with the falling edge of the clock.

REFERENCES:
patent: 5394373 (1995-02-01), Kawamoto
patent: 5400282 (1995-03-01), Suzuki et al.
patent: 5408438 (1995-04-01), Tanaka et al.

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