Multiplex communications – Wide area network – Packet switching
Patent
1993-07-02
1995-06-27
Hsu, Alpus
Multiplex communications
Wide area network
Packet switching
370 99, 370102, 370112, 375363, H04J 307, H04L 700
Patent
active
054286123
ABSTRACT:
A synchronous transmission system including a circuit arrangement for determining the data bytes of a signal to be received or to be transmitted. The circuit arrangement includes a control circuit (2, 14) which includes at least a counter (11, 19) for marking the pointer bytes of each high bit rate transport unit that can occur and which circuit arrangement includes at least a counter (6, 17) for marking with a count the data bytes of each high bit rate transport unit that can occur. The control circuit (2, 14) further includes for each group of low bit rate transport units that can occur in each maximum bit rate transport unit that can occur at least a position counter (6, 17), which counter is provided for marking with a count the data bytes in a low bit rate transport unit of the group. The control circuit (2, 14) is additionally provided at least for identifying the payload bytes and the pointer bytes on the basis of the counts and the information about the transport units of the signal.
REFERENCES:
patent: 5119406 (1992-06-01), Kramer
patent: 5168494 (1992-12-01), Mueller
patent: 5172376 (1992-12-01), Chopping et al.
patent: 5210745 (1993-05-01), Guinand et al.
patent: 5263056 (1993-11-01), Urbansky
patent: 5265090 (1993-11-01), Guinand et al.
patent: 5267239 (1993-11-01), Pospischil et al.
CCITT Recommendation G.709.
D. Peer, "Asic-Entwurf mit VHDL und Logiksynthese", Elektronik 23, 1991, pp. 84-92.
Leuschner Helmut
Niegel Michael
Scheffel Klaus
Barschall Anne E.
Hsu Alpus
U.S. Philips Corporation
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