Synchronous to non-synchronous data line pair interface apparatu

Multiplex communications – Wide area network – Packet switching

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Details

370 48, 370 91, 375118, H04J 306

Patent

active

051213923

ABSTRACT:
An algorithm is presented along with circuitry for implementing same to accomplish the interface of a pair of synchronized data lines with a pair of non-synchronized data lines using data buffers where there can be as few as three cells of data buffers to accomplish reading data out and writing data in without interfering one with the other. This algorithm is accomplished by measuring the time skew between overhead bits of the two non-syncrhonized data streams and writing to the frame most recently read by the synchronized data stream based on an algorithm formulated in view of or based on a function of the time skew.

REFERENCES:
patent: 3809820 (1974-05-01), Sullivan
patent: 4068098 (1978-01-01), Thyselivs
patent: 4665518 (1987-05-01), Champlin et al.
patent: 4941141 (1990-07-01), Hayano

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