Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-11-09
1999-10-05
Nelms, David
Static information storage and retrieval
Addressing
Sync/clocking
36523003, 365 2306, G11C 800
Patent
active
059635037
ABSTRACT:
A cache memory uses at least two synchronous memory devices operable of responding to an external clock signal and performing a bank operation mode. The memory device includes a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding to the internal clock signal, a first decoder generating a first selection signal to designate one of the second word lines and a second selection signal to designate one of the first word lines corresponding to the first word line which is preliminarily selected, a control signal generating circuit receiving the informing signal and generating a control signal responding to the internal clock signal, and a second decoder for receiving the first and second selection signals and for selecting the first word line, when the memory device is being selected. When the memory device goes to a selection state from a non-selection state, the control signal is enabled until the first and second selection signals are applied to the second decoder, during a cycle time of the informing signal.
REFERENCES:
patent: 5808959 (1998-09-01), Kengeri et al.
patent: 5812491 (1998-09-01), Shinozaki et al.
patent: 5835424 (1998-11-01), Kikukawa et al.
patent: 5848021 (1998-12-01), Sugibayashi
Nelms David
Nguyen Tuan T.
Samsung Electronic Co. Ltd.
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