Synchronous system for parallel data scrambling

Cryptography – Particular algorithmic function encoding

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380 33, 380 48, 380 46, 364717, H04K 100

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052673162

ABSTRACT:
Of the type formed by a pseudorandom code generator and a block that performs the synchronizing and the scrambling in parallel which, in addition to the initialization signal, receives as inputs the set of parallel input data and the codes generated by the code generator, and produces the scrambled parallel data at the outputs; the modulo-2 adders used in the feedback loops of the pseudorandom code generator have only two inputs, and the outputs of the code generator in the parallel working time slots tp and tp+1 are related through the expression:

REFERENCES:
patent: Re30957 (1982-06-01), Feistel
patent: 4520232 (1985-05-01), Wilson
patent: 4965881 (1990-10-01), Dilley
patent: 5010573 (1991-04-01), Musyck et al.
patent: 5031129 (1991-07-01), Powell et al.
patent: 5163092 (1992-10-01), McNesby et al.
patent: 5185799 (1993-02-01), McNesby et al.
"Parallel Scrambling Techniques for Digital Multiplexers" by DooWhon Choi, published in the Sep./Oct. 1986 AT&T Technical Journal, vol. 65, Issue 5, pp. 123-136.
"1-Gwords Pseudorandom Word Generator" by William J. McFarland, et al, IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 747-751.

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