Synchronous signal transfer and processing device

Details Synchronous signal transfer and processing device Synchronous signal transfer and processing device

2006-10-10

2006-10-10

Bocure, Tesfaldet (Department: 2611)

Pulse or digital communications

Synchronizers

C375S259000

Reexamination Certificate

active

07120214

ABSTRACT:
A transfer circuit includes a plurality of cascaded latch circuits. Two consecutive latch circuits in the transfer circuit complementarily enter a latching state and a transparent state in response to the applied clock signal, and data/a signal is transferred through the transfer circuit in response to the clock signal. A clock control circuit is provided for controlling an operation of each of the latch circuits. The clock control circuit detects that the latch circuit in a next stage of the corresponding latch circuit enters the latching state to permits transfer of the signal/data of the corresponding latch circuit to the subsequent stage in accordance with the corresponding clock signal. It is possible to prevent the data/signal from being transferred while the latch circuit at the next stage is in the transparent state to accurately transfer the data/signal. A clock synchronous data transfer and processing device reliably preventing racing is implemented with a simple circuit configuration.

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