Synchronous signal generation circuit

Details Synchronous signal generation circuit Synchronous signal generation circuit

2000-11-07

2002-01-08

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S210130

Reexamination Certificate

active

06337834

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-324201, filed Nov. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous signal generation circuit, particularly, to a synchronous signal generation circuit generating an internal clock signal in synchronism with an external clock signal supplied at a predetermined period, said internal clock signal being used for a high speed data transfer.
A In a conventional synchronous signal generation circuit, an internal clock signal is generated in synchronism with an external clock signal supplied to a memory device for use in a high speed data transfer. Since delay occurs in a circuit such as, for example, an input receiver in the input stage and in a circuit such as, for example, an off-chip driver in the output stage, the delay is corrected by using a synchronous circuit within the memory device.
FIG. 1
shows the construction of a conventional synchronous signal generation circuit including a mirror-type synchronous circuit as a main portion.
The synchronous signal generation circuit shown in
FIG. 1
comprises a real circuit including an input receiver
1
, a mirror-type synchronous circuit
2
and an off-chip driver
3
and a dummy circuit
6
a
surrounded by a dotted line and including an input receiver
4
and an off-chip driver
5
.
A small amplitude external clock signal n
0
a
supplied to the memory is inputted to the input receiver
1
of the real circuit, and a large amplitude signal n
1
a
of CMOS level is outputted from the input receiver
1
. In this case, a delay time D
1
r
occurs within the input receiver
1
.
The large amplitude signal n
1
a
of CMOS level is branched so as to be supplied both to the input receiver
4
of the dummy circuit
6
a
and to the mirror-type synchronous circuit
2
of the real circuit. In the path of the real circuit, the signal n
1
a
is transmitted through the mirror-type synchronous circuit
2
so as to be outputted from the mirror-type synchronous circuit
2
as a large amplitude signal n
4
a
of CMOS level. The signal n
4
a
is supplied to the off-chip driver
3
and is outputted from the off-chip driver
3
as a small amplitude internal clock signal n
5
a
. A delay time Dr
2
occurs within the off-chip driver
3
.
In the path of the dummy circuit
6
a
surrounded by the dotted line, the signal n
1
a
is supplied to the input receiver
4
of the dummy circuit
6
a, and a large amplitude signal n
2
a
of CMOS level is outputted from the input receiver
4
. The signal n
2
a
is supplied to the off-chip driver
5
, and a large amplitude signal n
3
a
of CMOS level is outputted from the off-chip driver
5
for driving the mirror-type synchronous circuit
2
. In this step, a delay time D
1
d
and another delay time D
2
d
occur in the input receiver
4
and the off-chip driver
5
, respectively.
In order to enable the synchronous signal generation circuit, which receives the external clock signal n
0
a
, to output the internal clock signal n
5
a
in synchronism with the external clock signal n
0
a
, it is necessary for the sum of the delay time of the external clock signal n
0
a
and the delay time of the internal clock signal n
5
a
to be exactly equal to an integral multiple of the period T of the external clock signal n
0
a
. An example, in which the sum of the delay time of the external clock signal n
0
a
and the delay time of the internal clock signal n
5
a
is equal to a single period, will now be described.
The input signal n
1
a
to the input receiver
4
is transmitted through the mirror-type synchronous circuit
2
via the path of the dummy circuit
6
a
. In this step, the input signal n
1
a
is triggered directly by the pulse rising edge of the pulse of the mirror-type synchronous circuit
2
, with the result that the delay time in the mirror-type synchronous circuit
2
is T−(D
1
d
+D
2
d
).
Incidentally, it should be noted that the mirror-type synchronous circuit
2
is constructed such that the upper and lower portions have the same structure. Therefore, if the mirror-type synchronous circuit
2
is constructed such that a delay time of T−(D
1
d
+D
2
d
) occurs when the signal passing through the dummy circuit
6
a
is transmitted through the upper portion of the mirror-type synchronous circuit
2
as denoted by a broken line, a delay time when the signal passing through the real circuit joined by a solid line is transmitted through the lower portion of the mirror-type synchronous circuit
2
as denoted by an arrow of a solid line is equal to T−(D
1
d
+D
2
d
). It follows that the sum of the delay time in the path of the real circuit is D
1
r
+T−(D
1
d
+D
2
d
)+D
2
r
. To make the sum of the delay time noted above equal to the period T and to obtain the internal clock signal n
5
a
in synchronism with the external clock signal n
0
a
, it is necessary for the delay times to meet the relationship D
1
r
+D
2
r
=D
1
d
+D
2
d
. In short, the delay time of the signal transmitted through the path of the dummy circuit must be equal to the delay time of the signal transmitted through the path of the real circuit excluding the mirror-type synchronous circuit. In other words, in order to allow the internal clock signal n
5
a
outputted from the synchronous signal generation circuit to be synchronized with the external clock signal n
0
a
, it is necessary for the delay time in the dummy circuit to imitate completely the delay time in the real circuit. Further, in terms of the manufacturing process, it is desirable for the relationships D
1
r
=D
1
d
and D
2
r
=D
2
d
to be satisfied.
FIG. 2
is a timing wave form diagram denoting the operation of the conventional synchronous signal generation circuit. The signal n
0
a
is a small amplitude external clock signal supplied to the input receiver
1
. The period T of the wave form of the signal n
0
a
is denoted by an arrow. The signal n
1
a
represents the output signal generated from the input receiver
1
. As shown in the drawing, the signal n
1
a
is inputted to the input receiver
4
of the dummy circuit
6
a
with a delay time D
1
r
and is outputted from the input receiver
4
as the large amplitude signal n
2
a
of CMOS level with a delay time D
1
d
. Further, the signal n
2
a
is inputted to the off-chip driver
5
of the dummy circuit
6
a
and is outputted from the off-chip driver
5
as a large amplitude signal n
3
a
of CMOS level with a delay time D
2
d.
The signal n
3
a
is inputted to the mirror-type synchronous circuit
2
. However, since the delay time of the signal n
3
a
is set at T−(D
1
d
+D
2
d
), the dummy output signal (not shown) transmitted through the mirror-type synchronous circuit
2
via the dummy circuit
6
a
is a signal delayed from the signal n
1
a
by a period T.
On the other hand, in the real circuit, the large amplitude output signal n
1
a
of CMOS level generated from the input receiver
1
is inputted to the mirror-type synchronous circuit
2
in which the delay time is set at T−(D
1
d
+D
2
d
), and the output signal n
4
a
generated from the mirror-type synchronous circuit
2
is inputted to the off-chip driver
3
and, then, outputted from the off-chip driver
3
as a small amplitude internal clock signal n
5
a
with a delay time D
2
r.
In the timing wave form shown in
FIG. 2
, the delay times T−(D
1
d
+D
2
d
) of the mirror-type synchronous circuit after transmission of the signal through the dummy circuit
6
a
and during transmission of the signal through the real circuit are denoted respectively as MIRROR by arrows. It should be noted that the small amplitude internal clock signal n
5
a
synchronized with the small amplitude external clock signal n
0
a
is outputted from the off-chip driver
3
with the delay time D
2
r from the rising edge of the signal n
4
a
. Incidentally,

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