Television – Synchronization – Sync separation
Reexamination Certificate
1998-06-30
2002-04-09
Harvey, David E. (Department: 2614)
Television
Synchronization
Sync separation
C348S525000
Reexamination Certificate
active
06369856
ABSTRACT:
BACK GROUND OF THE INVENTION
This invention relates to a liquid crystal display (LCD), and more particularly to a synchronous signal detection circuit for LCD capable of detecting vertical and horizontal synchronous signals from a composite synchronous signal with accuracy.
In general, vertical and horizontal synchronous signals is detected from a composite synchronous signal and displays video signals according to the detected vertical and horizontal synchronous signals on a LCD. In the prior, the vertical and horizontal synchronous signals have been detected from the composite synchronous signal by using a RC constant of a multivibrator. For example, as shown in
FIG. 1A
, the prior detection circuit generates trigger pulse at the rising and falling edges of an input pulse by using a delay means
11
and controls a bistable multivibrator
12
by the trigger pulse to detect the synchronous signals. The another detection circuit, as shown in
FIG. 1B
, drives the monostable multivibrator
14
by a rising trigger pulse generated from a delay means
13
to detect the synchronous signal having an adjustable pulse width. The another circuit, as shown in
FIG. 1C
, differentiates a rising trigger pulse from a monostable multivibrator
15
through a differential means
16
and then clips the differential pulse from the differential means
16
through a clipper
17
to detect the synchronous signal having a pulse width adjusted by the amplitude of the differential pulse and clipping level.
However, the above detection circuit has a disadvantage in that RC error is varied with an environment change such as temperature or a driving voltage, etc. and the delay time is varied, thereby varying the transition time. Furthermore, the prior detection circuit has a disadvantage in that the area for mounting and power consumption become large by using the RC element and multivibrator.
SUMMARY OF THE INVENTION
There is an object of the present invention to provide a synchronous signal detection circuit for LCD for detecting vertical and horizontal synchronous signals from a composite synchronous signal with accuracy with a digital logic construction.
There is another object of the present invention to provide a synchronous signal detection method for LCD for detecting vertical and horizontal synchronous signals from a composite synchronous signal with accuracy
According to an aspect of the present invention, there is provided to a synchronous signal detection circuit which detect a vertical synchronous signal and a horizontal synchronous signal from composite synchronous signal, comprising: a reset generation means for receiving an external composite synchronous signal and an external main clock signal to generate a reset signal at falling edge of the composite synchronous signal; a counter means being reset by the reset signal received from the reset generation means and for counting the main clock signal to generate first through fourth output signals; a vertical synchronous signal detection means for receiving the second output signal of the counter means and the composite synchronous signal to detect the vertical synchronous signal of the composite synchronous signal and generating the vertical synchronous signal; and a horizontal synchronous signal detection means for receiving the third and the fourth output signals of the counter means and the reset signal of the reset generation means to detect the horizontal synchronous signal of composite synchronous signal having a period of 1 horizontal scanning interval (1H).
The reset generation means includes a flip flop for toggling the composite synchronous signal externally received; a second flip flop which receives an output signal of the first flip flop and the main clock signal as an input signal and a clock signal; and an exclusive NOR gate for logically operating output signals of the first and second flip flops to generate the reset signal at a falling edge of the composite synchronous signal.
The counter means includes a counter which is reset by the reset signal of the reset generation mean and counts the main clock signal; and a decoder for decoding output signals of the counter to generate the first through the fourth output signals. The counter means generates the first through the fourth output signals every 1H and the first through third output signals are generated within ½H and the fourth output signal is generated between ½H and 1H.
The vertical synchronous signal generation means includes a flip flop which receives the composite synchronous signal as an input signal and is triggered at a falling edge of the second output signal of the counter means to generate the vertical synchronous signal as an output signal.
The horizontal synchronous signal generation means includes an first detection means for receiving the third and fourth output signals of the output signals from the counter means to detect a ½H interval of the composite synchronous signal and generating a detection signal; a second detection means for receiving an inverted signal of the detection signal from the first detection means and an inverted signal of the reset signal from the reset generation means to detect the horizontal synchronous signal in a 1H interval of the composite synchronous signal; a third detection means for receiving the detection signal of the first detection means and the inverted signal of the reset signal from the reset generation means to generate the horizontal synchronous signal in a ½H interval of the composite synchronous signal; and an output means for receiving output signals from the second and third detection means to output the horizontal synchronous signal having 1H period of the composite synchronous signal.
The first detection means includes a flip flop which receives the third and fourth output signals of the counter portion as a set signal and a reset signal to detect the ½H interval of the composite synchronous signal and generates the detection signal as an output signal. The second detection means includes an AND gate for receiving the inverted signal of the detection signal from the first detection means and the inverted signal of the reset signal from the first detection means to detect the horizontal synchronous signal having a 1H period in the 1H interval of the composite synchronous signal.
The third detection means includes a first means for receiving the detection signal of the first detection means and the inverted signal of the reset signal of the reset generation means to detect a horizontal synchronous signal having a ½H period in the ½H interval of the composite synchronous signal; a second means for dividing an output signal of the first means by two; and a third means for receiving output signals of the first means and the second means to generate the horizontal synchronous signal having a 1H period in the ½H interval of the composite synchronous signal.
In the third detection means, the first means includes a first AND gate for receiving the detection signal of the first detection means and the inverted signal of the reset signal from the reset generation means to detect the horizontal synchronous signal having a ½H period in the ½H interval of the composite synchronous signal. The second means includes a flip flop which receives the output signal of the first AND gate and an inverted signal of the third output signal of the counter means as an input signal and a reset signal to divide the output signal of the first AND gate. The third means for receiving output signals of the first AND gate and the flip flop to generate the horizontal synchronous signal having a 1H period in the ½H interval of the composite synchronous signal.
The output means includes a NOR gate for logically operating the first horizontal synchronous signal having a 1H period detected at the 1H interval of the composite synchronous signal through the second detection means and the second horizontal synchronous signal having a 1H period detected at the ½H
Harvey David E.
Hyundai DisplayTechnology Inc.
Selitto Behr & Kim
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