Synchronous semiconductor storage device

Details Synchronous semiconductor storage device Synchronous semiconductor storage device

2000-10-26

2002-02-19

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230010, C365S233500, C365S230080, C365S191000, C365S194000

Reexamination Certificate

active

06349071

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor storage device, and specifically to a synchronous semiconductor storage device in which the amount of current consumed in a standby mode is reduced.
2. Description of the Related Art
In recent years, along with the increase in operation speed of microprocessors, etc., demand for semiconductor storage devices which operate at higher speed has been growing. A semiconductor storage device developed for the purpose of meeting such a demand is a synchronous semiconductor storage device that operates in a synchronous burst operation mode. In such a storage device, high speed readout of data is achieved in addition to the increase in speed for normal random access, although an access method is limited to some extent.
The synchronous burst operation mode used in a clock synchronous semiconductor storage device is a high speed access mode in which predetermined data rows are sequentially output in synchronization with a system clock signal. One example of a synchronous semiconductor storage device which operates in a synchronous burst operation mode include a synchronous DRAM (hereinafter, referred to as “SDRAM”).
FIG. 8
shows an exemplary structure of an input circuit used in an SDRAM. This input circuit includes an internal clock activation signal generation circuit
52
which receives a system clock signal CLK and a clock activation signal CKE and outputs an internal clock activation signal &phgr;
51
, and an internal clock signal generation circuit
53
which generates an internal clock signal clk_in based on the internal clock activation signal &phgr;
51
and the system clock signal CLK.
FIG. 9
shows a structure of the internal clock activation signal generation circuit
52
which includes a pair of D-flip flop (D-FF) circuits
50
and
51
and an inverter INV
50
. The first D-FF circuit
50
receives a clock activation signal CKE at a data input terminal D, and a system clock signal CLK at a clock input terminal CK.
The first D-FF circuit
50
outputs a CKE latch output signal &phgr;
50
from its output terminal Q to a data input terminal D of the second D-FF circuit
51
. The second D-FF circuit
51
receives a system clock signal CLK at its clock terminal CK through the inverter INV
50
. The second D-FF circuit
51
outputs from its output terminal Q an internal clock activation signal &phgr;
51
to the internal clock signal generation circuit
53
.
FIG. 10
shows a structure of the internal clock signal generation circuit
53
. The internal clock signal generation circuit
53
includes an NAND gate NAND
54
and an inverter INV
55
. The NAND gate NAND
54
receives the internal clock activation signal &phgr;
51
from the internal clock activation signal generation circuit
52
, and the system clock signal CLK. The inverter INV
55
receives an output of the NAND gate NAND
54
. The internal clock signal generation circuit
53
outputs an output of the inverter INV
55
as an internal clock signal clk_in.
Operations of the input circuit having the above structure are described with reference to a timing chart as shown in FIG.
11
. Upon receiving the system clock signal CLK, the input circuit receives, at each rising edge of the pulse of the system clock signal CLK, a control signal and an address signal from outside in a time-division manner.
As shown in
FIG. 11
, the internal clock signal clk_in, which is used for receiving the control signal and the address signal, is controlled by the level of the clock activation signal CKE at each rising edge of the system clock signal CLK. Specifically, based on the level of the clock activation signal CKE at a rising edge of the system clock signal CLK, it is determined whether or not a pulse is generated as the internal clock signal clk_in in synchronization with a pulse of the system clock CLK in the subsequent clock cycle. For example, when the level of the clock activation signal CKE at a rising edge of the system clock signal CLK is a high level “H”, a pulse is generated as an internal clock signal clk_in in synchronization with a pulse of the system clock CLK in the subsequent clock cycle. When the level of the clock activation signal CKE at a rising edge of the system clock signal CLK is a low level “L”, a pulse of the internal clock signal clk_in is not generated in the subsequent clock cycle.
The generated internal clock signal clk_in is used as a synchronization signal in each of latch circuits
56
(
FIG. 12
) for latching an input address data signal and a control signal, etc., which are provided from outside. Each latch circuit
56
outputs the input address data signal and the control signal, etc., to the principal part of the semiconductor storage device in synchronization with the internal clock signal clk_in.
However, in a conventional internal clock activation signal generation circuit
52
, since the level of the clock activation signal CKE must be referred to at each rising edge of the system clock signal CLK, a large amount of electric current is consumed by a clock buffer of the internal clock activation signal generation circuit
52
which receives the system clock signal CLK. That is, switching of logic gates such as the first D-FF circuit
50
, the inverter INV
5
O, the NAND gate NAND
54
, etc., to which the system clock signal CLK is directly input, generates a discharge current due to a gate capacitance or a parasitic capacitance in a logic gate, etc., to which an output of a previous logic gate is supplied, in addition to the generation of a through-current. Thus, the amount of current consumed when the clock activation signal CKE is at a low level “L” and the semiconductor storage device is on standby cannot be reduced.
Especially when the frequency of the system clock signal CLK is increased, the current consumption is from about several hundreds of microamperes to about 1 mA. In a commonly-employed SDRAM, such an increase in current consumption is a significant problem.
Japanese Laid-Open Publication No. 7-177015 discloses a method for reducing the current consumption in the standby state of SDRAM. According to this method, when a first stage circuit, which receives external input signals used in the SDRAM except for the system clock signal CLK and the clock activation signal CKE, is on standby, power supply to the first stage circuit is stopped, whereby the current consumption is reduced.
However, such a method requires a level detection circuit for detecting the level of the clock activation signal CKE in order to detect the standby state, and it is required to incessantly supply the system clock signal CLK to the level detection circuit. Thus, as the frequency of the system clock signal CLK increases, the amount of current consumed by the level detection circuit increases.
Furthermore, Japanese Laid-Open Publication No. 11-16349 discloses a method for reducing the amount of current consumed when an internal operation of a storage device is on standby. According to this method, in the case where the clock activation signal CKE turns to a high level “H” and the internal operation is on standby, the internal clock signal is eliminated, whereby the current consumption is reduced.
However, according to such a method, in the case where the clock activation signal CKE is at a low level “L” and the internal operation is on standby, or in the case where a clock signal is adjusted to the operation frequency of an external system with which signals are exchanged, the current consumption cannot be reduced when the internal operation is in a clock suspend mode (which is an operation mode for memory access) by partially masking the clock signal so as to decrease the operation frequency.
Since a clock synchronous semiconductor storage device receives input signals at latch circuits in synchronization with rising edges of a system clock signal, the latch circuits each need to have received the system clock signal before or at the time of data input. Therefore, a conventional synchronous semiconductor storag

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