Synchronous semiconductor storage device

Details Synchronous semiconductor storage device Synchronous semiconductor storage device

1999-04-26

2001-01-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C203S014000

Reexamination Certificate

active

06175534

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor storage devices, and more particularly to synchronous semiconductor storage devices that receive external inputs signals synchronously with an external clock signal.
BACKGROUND OF THE INVENTION
Many types of integrated circuits, including conventional synchronous semiconductor storage devices, are subject to various types of testing. One type of reliability test is an accelerated (burn-in) test. Burn-in tests are typically carried out after a device in “die” form has been assembled into a package. To reduce the time required to conduct burn-in testing, it is known to test a number of semiconductor storage devices in parallel. Unfortunately, due to the high load presented by multiple parallel devices, testing signals applied to the devices have a relatively low frequency. Thus, the parallel testing of synchronous storage devices can be more problematic than asynchronous semiconductor storage devices, as it can take a relatively long time to access the memory cells. Longer testing times can result.
Referring now to
FIG. 6
, a schematic diagram is set forth illustrating a conventional synchronous semiconductor storage device. A portion of a synchronous semiconductor storage device is designated by the general reference character
600
, and is shown to include a number of control input receivers
602
-A to
602
-D, each of which receives corresponding control signals (shown as RASB, CASB, WEB, and ADD). In response to the various control signals (RASB, CASB, WEB, and ADD), the control input receivers (
602
-A to
602
-D) apply corresponding internal signals to mode register setting circuit
604
. According to a predetermined set of internal signals, the mode register setting circuit
604
can generate a test mode activating signal (TEST_MODE).
Also set forth in
FIG. 6
is a clock signal input receiver
606
and a select signal input receiver
608
. The clock signal input receiver
606
is shown to receive a clock signal CLK while the select signal input receiver
608
is shown to receive a select signal CSB. The output of the clock input receiver
606
is applied to a pulse generator circuit
610
that generates an internal clock signal ICLK. The output of the select input receiver
608
is applied to another pulse generator circuit
612
to generate an internal select signal CSCLK. The output of the select input receiver
608
is also applied as an input to an OR gate
614
. The OR gate
614
also receives the TEST_MODE signal as another input.
The pulse generator circuit
612
also receives the TEST_MODE signal. In the particular arrangement of
FIG. 6
, t he TEST_MODE signal enables the pulse generator circuit
612
.
The outputs of pulse generator circuits
610
an d
612
(the ICLK and CSCLK signals) are applied as inputs to an OR gate
618
. The output of OR gate
618
is another clock signal ICLK′. The ICLK′ signal is applied to the mode register setting circuit
604
as well as other internal circuits
616
.
When a test mode is entered (TEST_MODE is activated), the ICLK′ signal is generated by the CLK signal pulsing high and the CSB signal pulsing high. A first ICLK pulse is generated by pulse generating circuit
610
. A second CSCLK pulse is generated by pulse generating circuit
612
. An OR gate combines the two pulses to generate an ICLK′ signal that pulses at twice the frequency of the memory tester (pulses twice the frequency of the CLK signal as applied during bun-in). In this way, an ICLK′ signal can be generated for those circuits that would otherwise receive the ICLK signal in a non-test mode. This allows for faster testing, thereby overcoming the slow testing arising out of conventional parallel testing approaches.
It is noted that in a non-test mode (TEST_MODE signal inactive), the ICLK′ signal includes pulses generated synchronously with the CLK signal, as pulse generating circuit
612
will be disabled. The ICLK′ signal is then applied to internal circuits
616
and mode register setting circuit
604
to control the timing of such circuits.
While the conventional approach of
FIG. 6
is capable of generating an internal clock signal ICLK′ having a frequency faster than that of an applied external clock signal CLK, such an arrangement can have drawbacks. In many synchronous semiconductor storage devices it is necessary to execute a mode register setting operation to initialize a device after power has been applied to the device. Such an operation involves applying a particular set of signals (e.g., RASB, CASB, WEB or ADD) on the rising edge of a clock signal (CLK).
A drawback to the approach illustrated by
FIG. 6
can best be understood with reference to a timing diagram set forth in FIG.
7
.
FIG. 7
illustrates the responses of the CLK, CSB, ICLK′, RASB, CASB, WEB, and ADD signals. In the operation illustrated by
FIG. 7
, the CSB signal transitions low before the mode register has been set. With the CSB signal low, the CLK signal then transitions high. In response to the transition of the CLK signal, the ICLK signal is pulsed high by the pulse generator
610
. The ICLK pulse is translated into a first ICLK′ pulse by OR gate
618
. The first ICLK′ pulse latches the RASB, CASB, WEB and ADD values. The latched RASB, CASB, WEB and ADD signals will place the device in the desired mode of operation. However, due to the advantageous “double frequency” capability of the circuit, a second ICLK′ high-going transition in the CSB signal. By the time the second ICLK′ pulse transitions high, the RASB, CASB, WEB and ADD values have changed. Consequently, the second ICLK′ pulse latches unintended RASB, CASB, WEB and ADD values in a mode register setting circuit, placing the device in an unintended mode of operation.
The latching of unintended mode setting values can be particularly problematic if the device is in a test mode. For example, if a device is placed in a test mode after applying power to the device, it is desirable to be able to take the device out of the test mode by applying a combination of mode setting signals (RASB, CASB and WEB) that indicate a non-test mode. However, if the CSB signal is shifted to transition high immediately after the application of a mode register setting command, but prior to the transmission of non-test mode control signal values, erroneous latching of mode setting values can take place. Therefore, while an approach such as that set forth in
FIG. 6
can provide for advantageously fast test clock signals, such an approach can also provide disadvantageous results for mode register setting circuits and the like.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous semiconductor device that can shorten a test time when used in a tester having a relatively low clock frequency, and also transition to a desired mode of operation after entering a test mode of operation.
According to the disclosed embodiments, a synchronous semiconductor storage device can include a first input receiver for receiving a first external clock signal and a second input receiver for receiving a second external clock signal. A first pulse generating circuit receives the output of the first input receiver and provides a first internal synchronous signal in response thereto. A second pulse generating circuit receives the output of the second input receiver and provides a second internal synchronous signal in response thereto. A logic gate generates a third internal synchronous signal in response to the outputs of the first input receiver and the second input receiver. In a test mode, a mode register setting circuit can output an active test mode activating signal synchronously with the first internal synchronous signal. An internal circuit receives the third internal synchronous signal.
According to one aspect of the embodiments, when the test mode activating signal is not active, an internal circuit operates synchronously with the first internal synchronous signal. When t

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