Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-29
2001-05-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S203000
Reexamination Certificate
active
06240049
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous semiconductor storage device whose internal circuit operates in synchronization with a system clock.
Conventionally, as a synchronous semiconductor storage device, there is a synchronous masked ROM that operates at a system clock of 100 MHz according to the control timing shown in
FIGS. 13A through 13I
. In this synchronous masked ROM (referred to as a ‘synchronous MROM’ hereinafter), a word line is made to rise, or turned on after the input of a row address, and a desired column selector is enabled after the input of a column address shown in
FIG. 13B
, to charge selected bit lines
1
and
2
shown in
FIGS. 13E and 13H
and a virtual GND line up to a precharge level on the basis of precharging timings
1
and
2
shown in
FIGS. 13C and 13G
, respectively (the first and second stages in two cycles). Next, in each cycle, the bit line sensing, or the bit line drawing by the selected memory cell, is performed (the third stage). Next, a potential difference between the bit line and a reference line is amplified by a sense amplifier when the sense amplifier enabling signal SAE
1
, SAE
2
(shown in
FIGS. 13D and 13I
) has an H-level (the fourth stage). Finally, data CA
0
, CA
1
, . . . shown in
FIG. 13F
are sequentially output (the fifth stage). The CAS latency in this case is five. The term ‘CAS latency’ means the number of cycles of a clock CK (shown in
FIG. 13A
) from the input of a column address that is an input command, to the output of read data.
As described above, in the aforementioned synchronous MROM, the memory cell reading operation and the precharge operation of the bit line and the virtual GND line are independently executed.
According to the control timing of the synchronous MROM, five clock pulses are necessary during the time from the column address input to the read data output (namely, CAS latency: 5). In contrast to this, the operation of a synchronous dynamic RAM (referred to as a ‘synchronous DRAM’ hereinafter) has a CAS latency of 2 or 3 from the column address input to the read data output when the system clock of 100 MHz is used. That is, in the synchronous DRAM, the read data is output in 20 ns or 30 ns from the column address input. In contrast to this, the synchronous MROM generally has a CAS latency of 5 (or 6) from the column address input to the read data output when the system clock of 100 MHz is used. That is, in the synchronous MROM, the read data is output in 50 ns (or 60 ns) from the column address input.
As described above, the synchronous MROM, in which the memory cell read operation and the precharge operation of the bit lines and the virtual GND line are independently executed, has a CAS latency of 5, meaning that the access becomes slower than that of the synchronous DRAM. Therefore, in a system using both the synchronous MROM and the synchronous DRAM, system performance disadvantageously deteriorates by the synchronous MROM that has a longer access time.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a synchronous semiconductor storage device capable of executing a read operation in an access time equivalent to that of the synchronous DRAM without increasing a standby current nor an operating current.
In order to accomplish the object, a synchronous semiconductor storage device comprises:
a plurality of memory blocks into which a plurality of memory cells arranged in a matrix form have been divided every plural number of columns;
word lines each activating the memory cells of an identical row in each memory block;
bit lines each connected to one terminal of the memory cells of an identical column of each memory block;
virtual GND lines each connected to the other terminal of the memory cells of an identical column of each memory block;
a column selector that selects any one of the memory blocks on the basis of an input column address in a read operation;
a sense amplifier that holds and amplifies a signal representing a level difference between a reference line and the bit line of the memory block selected by the column selector;
a precharge level supply circuit that supplies a precharge level to the bit lines and the virtual GND lines of the memory blocks other than the memory block selected by the column selector; and
a disconnecting circuit that, upon latching of the signal representing the level difference between the reference line and the bit line by the sense amplifier in the read operation, disconnects the bit line and the reference line from the sense amplifier until a next read operation and also disconnects the virtual GND line from the ground potential until the next read operation.
In the synchronous semiconductor storage device having the above construction, the charging (precharge operations) of all the bit lines and all the virtual GND lines has been completed by the precharge level supply circuit at the time when the word line for activating memory cells has risen, or has been turned on. Next, any one of the memory blocks is selected from the plurality of memory blocks by the column selector on the basis of the input column address, and the bit line sense (drawing) operation is executed in the selected memory block (the first stage). In the bit line sense operation, the potential, or level, of the bit line lowers if the memory cell being read is a transistor in an on state, while the bit line maintains the precharge level if the memory cell being read is a transistor in an off state. Next, after the signal representing the potential difference between the bit line and the reference line gets held or latched by the sense amplifier, then the bit line and the reference line that have been connected to the sense amplifier and the virtual GND line that have been connected to the ground potential are disconnected from the sense amplifier and the ground potential, respectively, by the disconnecting circuit until the next read operation, and the signal representing the retained level difference is amplified by the memory sense amplifier (the second stage). In this stage, the precharge level supply circuit supplies the precharge level to the bit lines and the virtual GND lines disconnected by the disconnecting circuit, making all the bit lines and all the virtual GND lines again have the precharge level. Then, the data amplified by the sense amplifier is output (the third stage). As described above, by completing the precharging of all the bit lines and all the virtual GND lines before the column address input and executing parallel the precharge operation of the bit lines and the virtual GND lines and the amplifying operation by the sense amplifier in the read operation, the CAS latency of 3 that is the same as that of the synchronous DRAM is achieved. Thus, in a system using both the synchronous DRAM and the synchronous MROM, the throuput can be improved. In addition, the precharge levels of all the bit lines and all the virtual GND lines are consistently maintained before the column address input. Accordingly, it is possible to realize a synchronous semiconductor storage device that can execute the read operation in an access time equivalent to that of the synchronous DRAM, without increasing the standby current nor the operating current.
In one embodiment, the precharge level supply circuit retains all the bit lines and virtual GND lines at the precharge level in a standby stage, and in the read operation, stops supplying the precharge level to the bit lines and the virtual GND lines of the memory block selected by the column selector while retaining the precharge level of the bit lines and the virtual GND lines of the memory blocks other than the selected memory block. The bit line sensing (drawing) for the memory cell is thus achieved in the first stage.
In one embodiment, the synchronous semiconductor storage device further comprises:
a normal precharge level generating circuit that forms a normal precharge level to be supplied to the bit lines and the virtual GND lines;
a power-on stage precharge level
Morrison & Foerster / LLP
Nelms David
Sharp Kabushiki Kaisha
Tran M.
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