Synchronous semiconductor memory having a write execution time d

Details Synchronous semiconductor memory having a write execution time d Synchronous semiconductor memory having a write execution time d

1996-11-12

1999-02-02

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518905, G11C 800

Patent

active

058674470

ABSTRACT:
In a synchronous semiconductor memory, there is provided a write pulse generating circuit receiving a pipeline enable signal, a write enable signal and an internal synchronous signal which is generated by delaying an output of an internal synchronous signal generating circuit by a first delay. This write pulse generating circuit includes a second delay, and is configured to generate a write pulse which is put into an inactivate condition for a constant time corresponding to a delay time of the second delay when the internal synchronous signal is brought to a high level, and thereafter, is maintained in an activate condition until the next internal synchronous signal is supplied. Thus, by adjusting the delay amount of the first delay and the delay amount of the second delay, a column selection line is never switched during a period that a write data is being supplied to write bus pairs, so that the write data is accurately written into a sense amplifier. Thus, the write execution time depends upon the cycle time, with the result that the cycle time for the writing can be shortened.

REFERENCES:
patent: 5293347 (1994-03-01), Ogawa
patent: 5341341 (1994-08-01), Fukuzo
patent: 5576996 (1996-11-01), Awaya et al.
patent: 5581512 (1996-12-01), Kitamura
patent: 5617361 (1997-04-01), Sugawara

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