Synchronous semiconductor memory device with low power consumpti

Details Synchronous semiconductor memory device with low power consumpti Synchronous semiconductor memory device with low power consumpti

1995-08-08

1997-03-04

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Sync/clocking

39549701, 39549704, 395494, 395432, 395467, G11C 800

Patent

active

056086865

ABSTRACT:
A synchronous semiconductor memory device has an M-bit I/O configuration memory device mode and an M.times.2.sup.k -bit I/O configuration memory device mode. In the former mode, n bits whose transition frequencies are smaller are selected from an m-bit internal address and are used to access a memory section, while the other k (=m-n) bits whose transition frequencies are larger are selected from the m-bit internal address to select one of 2.sup.k groups of internal data lines of the memory section and connect them to some of data input/output pins. In the latter mode, n bits whose transition frequencies are larger are selected from the m-bit internal address and are used to access the memory section, while the 2.sup.k groups of the data lines are connected to all the data input/output pins.

REFERENCES:
patent: 5546346 (1996-08-01), Abata et al.
patent: 5550784 (1996-08-01), Takai

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