Synchronous semiconductor memory device with a plurality of...

Details Synchronous semiconductor memory device with a plurality of... Synchronous semiconductor memory device with a plurality of...

2005-04-26

2005-04-26

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S191000, C365S201000, C365S233100

Reexamination Certificate

active

06885606

ABSTRACT:
A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks, bank select circuits which activate a second control signal to activate each of the memory banks, and bank timer circuits which deactivate the activated second control signal and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.

REFERENCES:
patent: 5966725 (1999-10-01), Tabo
patent: 6088291 (2000-07-01), Fujioka et al.
patent: 6275895 (2001-08-01), Tabo
patent: 6453370 (2002-09-01), Stracovsky et al.
patent: 9856004 (1998-12-01), None

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