Synchronous semiconductor memory device suitable for merging wit

Details Synchronous semiconductor memory device suitable for merging wit Synchronous semiconductor memory device suitable for merging wit

1999-01-13

2000-10-17

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523008, 36523003, G11C 800

Patent

active

061341789

ABSTRACT:
Pre-amplifier circuits latch circuits, and output circuits respectively corresponding to a plurality of memory arrays are provided, and a data bus is provided common to these output circuits. The data bus provided extending in the column-direction over a memory array. Thus, a synchronous semiconductor memory device adapted for merging a logic and allowing the data bus width to be readily expanded without increasing the area occupied by interconnections and without conflicts of interconnections can be provided.

REFERENCES:
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5892730 (1999-04-01), Sato et al.
patent: 5926434 (1999-07-01), Mori
patent: 5946266 (1999-08-01), Iwamoto et al.

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