Synchronous semiconductor memory device reliably fetching extern

Details Synchronous semiconductor memory device reliably fetching extern Synchronous semiconductor memory device reliably fetching extern

1997-09-04

1998-12-01

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523006, 3652335, G11C 800

Patent

active

058448594

ABSTRACT:
When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.

REFERENCES:
patent: 5404338 (1995-04-01), Murai et al.
patent: 5517462 (1996-05-01), Iwamoto et al.
patent: 5546355 (1996-08-01), Raatz et al.
patent: 5691955 (1997-11-01), Yamauchi
patent: 5764584 (1998-06-01), Fukiage et al.

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