Synchronous semiconductor memory device performing input/output

Details Synchronous semiconductor memory device performing input/output Synchronous semiconductor memory device performing input/output

1997-01-07

1998-03-10

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 800

Patent

active

057269505

ABSTRACT:
An input circuit 200 includes first to fourth switching transistors T1-T4 to be controlled by clock signals CLK and /CLK, and two latch circuits 202 and 204. In response to a rising edge of the clock signal, switching transistor T1 is turned on, and latch circuit 202 takes in data. In response to a falling edge of clock signal CLK, switching transistor T3 is turned on, and latch circuit 204 takes in the data. Since input and output of the data are performed at both the rising edge and the falling edge of the clock signal, the operation can be performed at double the frequency.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5404338 (1995-04-01), Murai et al.
patent: 5517459 (1996-05-01), Ooishi
patent: 5592434 (1997-01-01), Iwamoto et al.
"A 32K WORD .times.32-Bit Synchronous Burst SRAM", Shigeki OHBAYASHI et al. Mitsubishi Denki Giho: vol. 69, No. 6 pp. 78-83 (1995) no month.

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