Synchronous semiconductor memory device operating in synchroniza

Details Synchronous semiconductor memory device operating in synchroniza Synchronous semiconductor memory device operating in synchroniza

1996-05-23

1997-11-25

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523008, 365236, G11C 700

Patent

active

056919557

ABSTRACT:
A synchronous semiconductor memory device according to the present invention is provided with two column address counters corresponding to two banks. The two column address counters receives two reference internal column address signals output from the two column address buffers. Each of the column address counters outputs internal column address signals successively and alternately according to the reference internal column address signals. As a result, when the access is to be performed alternately to the two banks, it would not be necessary to input an external column address signal each time the bank to be accessed changes, so that it is made possible to simplify the address input.

REFERENCES:
patent: 4773049 (1988-09-01), Takemae
patent: 5274596 (1993-12-01), Watanabe
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5539696 (1996-07-01), Patel
Yunho Choi et al, 16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate, VSLI Circuit Symposium 1993, pp. 65-66.

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