Synchronous semiconductor memory device operable in a snooze mod

Details Synchronous semiconductor memory device operable in a snooze mod Synchronous semiconductor memory device operable in a snooze mod

1995-07-21

1997-02-11

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365195, 365196, G11C 700

Patent

active

056027982

ABSTRACT:
A synchronous semiconductor memory device includes a clock input circuit receiving an externally applied clock signal to produce an internal clock signal, a signal input circuit taking in an externally applied signal to produce an internal signal, a first delay circuit delaying an externally applied snooze mode signal by a first delay time for supplying to a clock input circuit, and a second delay circuit delaying the externally applied snooze mode signal by a second delay time for supplying to the signal input circuit. The clock input circuit and the signal input circuit are disabled when the internal snooze mode signal is active. The semiconductor memory device takes in the external signal and produces an internal signal in synchronization with the internal clock signal. Upon switching over to the snooze mode, the operation is performed in accordance with the external signal in the cycle in which the snooze mode is designated, and the internal operation is inhibited in the subsequent cycles. Upon release from the snooze mode, the internal clock signal is produced in the cycle subsequent to the cycle in which the release from the snooze mode is designated, and the signal input circuit is enable in and after the clock cycles subsequent to the cycle in which the internal clock signal is produced.

REFERENCES:
patent: 5490116 (1996-02-01), Tobita et al.

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