Synchronous semiconductor memory device operable in a plurality

Details Synchronous semiconductor memory device operable in a plurality Synchronous semiconductor memory device operable in a plurality

1997-12-01

1999-04-06

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523003, G11C 800

Patent

active

058927301

ABSTRACT:
A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.

REFERENCES:
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5568445 (1996-10-01), Park et al.
patent: 5815462 (1998-09-01), Konishi et al.
"A 25ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay", Saeki et al., ISSCC96, Session 23, DRAM Paper SP 23.4, Feb. 10, 1996.

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