Synchronous semiconductor memory device operable in a burst mode

Details Synchronous semiconductor memory device operable in a burst mode Synchronous semiconductor memory device operable in a burst mode

1998-04-17

1999-11-23

Le, Vu A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365233, G11C 700

Patent

active

059912235

ABSTRACT:
Predetermined bits of an address signal taken into an address register are taken into a burst address counter and are changed in synchronization with a clock signal. The address bits from the burst address counter are applied to a block decoder for selecting a memory sub-array from the plurality of memory sub-arrays. A block address and the memory sub-array to be selected change at every clock cycle. An operation frequency of data read circuits provided for the respective memory sub-arrays can be made lower than a frequency of the clock signal. Memory cell data can be read out accurately even in a high-frequency operation.

REFERENCES:
patent: 5619456 (1997-04-01), McClure
patent: 5822254 (1998-10-01), Koshikawa et al.
"A 167MHz 1-Mbit CMOS Synchronous Cache SRAM", H. Yahata et al., IEICE Transaction on Electronics, vol. E80-C, No. 4, Apr. 1997, pp. 557-565.

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