Synchronous semiconductor memory device having stable data...

Details Synchronous semiconductor memory device having stable data... Synchronous semiconductor memory device having stable data...

2005-07-26

2005-07-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000

Reexamination Certificate

active

06922372

ABSTRACT:
In a delay adjusting unit arranged in a clock delay adjusting circuit, when a drive power switch signal is at an “H” level, a transfer gate is closed, and an input signal is delayed by a delay amount of the delay unit. When drive power switch signal is at the “L” level, the transfer gate is closed, and the input signal is output without being delayed. When the current drive power of an output buffer is low, the drive power switch signal at the “L” level decreases the delay amount of an output clock signal. When the current drive power is high, the drive power switch signal at the “H” level increases the delay amount of the output clock signal.

REFERENCES:
patent: 6301191 (2001-10-01), Ooishi
patent: 6333892 (2001-12-01), Hamamoto et al.
patent: 10-308096 (1998-11-01), None
patent: 2003-085974 (2003-03-01), None

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