Synchronous semiconductor memory device having input circuit...

Details Synchronous semiconductor memory device having input circuit... Synchronous semiconductor memory device having input circuit...

2000-03-29

2001-02-13

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C365S194000, C365S195000, C365S227000, C365S222000

Reexamination Certificate

active

06188641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to synchronous semiconductor memory devices which input and output signals in synchronization with a clock, more particularly, to SDRAMs (synchronous random access memories) having input circuits with reduced power consumption.
2. Description of the Related Art
Since DRAM is of a high storage density but consumes a large amount of power compared with SRAM, reduction in power consumption has been demanded.
FIG. 9
is a wiring diagram between a SDRAM controller
10
and a plurality of SDRAMs
11
to
14
.
The SDRAM controller
10
decodes the higher order 2-bits of an address provided thereto to produce chip select signals *CS
1
to *CS
4
, and further not only divides the address except the higher order 2 bits into row and column addresses (ADDR) to perform time-division multiplex, but also generates the row address strobe signal RAS and the column address strobe signal CAS in relation to the row and column addresses. The RAS and CAS signals constitute a multi-bit command CMD together with the write enable signal WE. The SDRAM controller
10
sets the clock enable signal CKE high, which is used for generating an internal clock through an AND operation with an external clock CLK, prior to selection of one of SDRAMs
11
to
14
.
The SDRAMs
11
to
14
are connected to a microprocessor not shown through the SDRAM controller
10
. The chip select signal outputs *CS
1
to *CS
4
of the SDRAM controller
10
are respectively connected to the chip select signal inputs *CS of the respective SDRAMs
11
to
14
, and the outputs of the external clock CLK, command CMD, DATA, address ADDR and clock enable signal CKE of the SDRAM controller
10
are commonly connected to corresponding terminals of the SDRAMs
11
to
14
.
When the signals *CS
1
to *CS
4
are all high and thereby all the SDRAMs
11
to
14
are not selected, the clock enable signal CKE is set low to stop the internal clock in each of the SDRAMs
11
to
14
, whereby the input circuits that synchronizes an input with the internal clock becomes deactivate, resulting in reducing consumption of power in each of the SDRAMs
11
to
14
.
However, as shown in
FIG. 10
for example, when only the SDRAM
11
of the SDRAMs
11
to
14
is selected by setting only the chip select signal *CS
1
to low while the signals *CS
2
to *CS
4
are kept high, power is wasted in the non-selected SDRAMs
12
to
14
since the clock enable signal CKE is set high prior to the selection of the SDRAM
11
and thereby the internal clocks in the SDRAMs
12
to
14
operate and thus the input circuits thereof are activated.
In order to avoid this inconvenience, if independent clock enable signals are provided to the respective SDRAMs
11
to
14
, the number of interconnections increases and a configuration of wiring becomes complicated.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a synchronous semiconductor memory device enabling reduction in useless power consumption of input circuits with no increase in the number of external interconnections.
In the present invention, there is provided a synchronous semiconductor memory device comprising: a command input circuit, for latching an external command in synchronization with an internal clock; and a command decoder, for decoding the latched external command; a chip select signal input circuit, receiving an external chip select signal, for activating an enable signal in response to activation of the external chip select signal, for deactivating the enable signal in response to deactivation of the external chip select signal, for generating an internal chip select signal by synchronizing the external chip select signal with the external clock; a clock input circuit, for outputting the internal clock depending on the external clock while the enable signal is active; and a decode enabling circuit, for generating a command decoder activating signal by synchronizing the internal chip select signal with the internal clock.
With the present invention, when the internal chip select signal is active, the command decoder activating signal is generated in synchronization with the internal clock and operation is performed depending on the decoded result of the command decoder, therefore it is not necessary to use the prior art clock enable signal. Further, when the external chip select signal is inactive, the enable signal is inactive, thereby the clock input circuit and the command input circuit of a non-select synchronous semiconductor memory device is inactive, resulting in decreasing in power consumption of the memory device.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 5767712 (1998-06-01), Takemae et al.
patent: 6009039 (1999-12-01), Takemae et al.
patent: 7-230688 (1995-08-01), None

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