Synchronous semiconductor memory device having input buffers...

Details Synchronous semiconductor memory device having input buffers... Synchronous semiconductor memory device having input buffers...

2000-05-12

2001-07-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080

Reexamination Certificate

active

06256260

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a synchronous semiconductor memory device having external signal input buffers and latch circuits, capable of improving an operational speed thereof and reducing power consumption.
DESCRIPTION OF THE PRIOR ART
For achieving a high speed of operation in a semiconductor memory device, synchronous semiconductor memory devices have been developed. The synchronous semiconductor memory device operates in synchronization with an external cock signal. The synchronous semiconductor memory device includes a synchronous dynamic random access memory (SDRAM), a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM and the like.
Generally, a synchronous semiconductor memory device includes a plurality of external signal input buffers and latch circuits. The external signal input buffers receives external signals to generate internal signals which can be used within the semiconductor memory device. The latch circuits latches and outputs the internal signals to the internal circuits.
A clock buffer, one of the external signal input buffers, receives an external clock signal to output a buffered clock signal and an internal clock signal generator generates an internal clock signal in response to the buffered clock signal. Other external signal input buffers receive external signals to output buffered signals. Then, the latch circuits latch and output the buffered signals, as internal signals, from the external signal input buffers to the internal logic circuits in response to the internal clock signal. Therefore, the synchronous semiconductor memory device operates in synchronization with the internal clock signal.
Hereinafter, conventional input buffers and latch circuits used in a synchronous semiconductor memory device are described with reference with
FIGS. 1 and 2
.
Referring to
FIG. 1
, a clock buffer
100
receives an external clock signal CLK to output a buffered clock signal, and an internal clock generator
102
generates an internal clock signal CLK_PULSE in response to the buffered clock signal.
A plurality of external signal input buffers
104
,
106
A to
106
C and
108
A to
108
D receive respective external signals to output buffered signals having a predetermined level which can be used in internal logic circuits. Here, the external signals includes a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and external address signals ADD<
0
> to ADD<N>. For example, a CS buffer
104
receives an external chip select signal CS to output a buffered chip select signal and an inverted chip select signal.
Then, the latch circuits
110
A to
110
N latches and outputs each buffered signal and inverted buffered signal in response to the internal clock signal CLK_PULSE from the internal clock generator
102
. Here, a reference numeral CS_OUT, for example, represents an internal chip select signal synchronized with the internal clock signal CLK_PULSE, and CS_OUTZ an inverted internal chip select signal.
FIG. 2
is a timing chart of signals shown in
FIG. 1. A
reference numeral LAT_OUT represents an output signal from one latch circuit, synchronized with the internal clock signal CLK_PULSE, LAT_OUTZ an inverted output signal from the latch circuit, synchronized with the internal clock signal CLK_PULSE. The external signal includes a chip select signal CS, a row address strobe signal RAC, a column address strobe signal CAS, a write enable signal, WE, and address signals ADD<
0
> to ADD<N>.
Referring to
FIG. 2
, in case where the external clock signal CLK is at a rising edge and the chip select signal CS is low, the internal clock signal CLK_PULSE is generated and the internal clock signal CLK_PULSE is applied to the latch circuits. The latch circuits latches and outputs the buffered signal LAT_OUT and the inverted buffered signal LAT_OUTZ, synchronized with the internal clock signal CLK_PULSE.
Although the buffered signals and the inverted buffered signals from the input buffers are transferred to the latch circuits, however, the buffered signals and the inverted buffered signals can not be transmitted to the internal logic circuits until the internal clock signal CLK_PULSE from the internal clock generator
102
is transmitted to each latch circuit. Therefore, the conventional semiconductor memory device has a disadvantage that an operating speed is reduced.
Furthermore, since the identical clock signal CLK_PULSE is subject to a level transition, e.g., rising edge or falling edge, of the external clock signal CLK, even after the external signals are transmitted to the internal logic circuits of the semiconductor memory device, the latch circuits
110
A to
110
N responsive to the internal clock signal CLK_PULSE are unnecessarily turned on and off in response to the external signals and the internal clock signal CLK_PULSE, thereby increasing an undesirable power consumption, as shown in section A of FIG.
2
.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a synchronous semiconductor memory device having external signal input buffers and latch circuits, in which the latch circuits are controlled by a latch control signal obtained by using the internal chip select signal from the chip select signal buffer, thereby decreasing a delay time required to transfer the external signals to an internal logic circuit and reducing an unnecessary power consumption.
In accordance with an aspect of the present invention, there is provided a synchronous semiconductor memory device having a plurality of external signal input buffer and a plurality of latch circuits, comprising: a clock buffer means for receiving an external clock signal to generate a buffered clock signal; a chip select buffer means for receiving an external chip select signal and the buffered clock signal from said clock buffer means to generate a buffered chip select signal, an inverted buffered chip select signal and a latch control signal, wherein the latch control signal is activated when the external clock signal is at the rising edge and the external chip select signal is low; a plurality of external signal buffer means for receiving external signal to generate buffered signals and inverted buffered signals; and a plurality of latch means for latching and outputting the buffered signals and the inverted buffer signals to an internal logic circuit in response to the latch control signal.


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