Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-04-13
1999-10-19
Hoang, Huan
Static information storage and retrieval
Addressing
Sync/clocking
36523003, 365195, G11C 800
Patent
active
059700211
ABSTRACT:
A reset signal generation circuit included in an output control circuit ANDs a reset signal for resetting complementary data buses for transferring data to a second output stage at prescribed timing and an internal control signal corresponding to a read mask signal and outputs a reset signal for resetting other complementary data buses for transferring the data to a final output stage. Thus, invalid data is reset on the complementary data buses.
REFERENCES:
patent: 5777942 (1998-07-01), Dosaka et al.
Hoang Huan
Mitsubishi Denki & Kabushiki Kaisha
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