Synchronous semiconductor memory device having burst access mode

Details Synchronous semiconductor memory device having burst access mode Synchronous semiconductor memory device having burst access mode

1999-09-30

2000-08-29

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365233, 365236, 36523008, 36523003, G11C 810

Patent

active

061118109

ABSTRACT:
The present invention provides a synchronous memory device having at least a multi-bit pre-fetch address generator circuit, and at least an access path which includes at least a command decoder having an output terminal connected to at least a follower circuit element which receives a command signal from the at least a command decoder, wherein the at least a multi-bit pre-fetch address generator circuit is connected to the at least a follower circuit element in parallel to the at least a command decoder, so that the at least a multi-bit pre-fetch address generator circuit is excluded from a transmission path of the command signal, whereby the at least a multi-bit pre-fetch address generator circuit generates a plurality of internal address signals independently from transmission of the command signal from the at least a command decoder to the at least a follower circuit element.

REFERENCES:
patent: 5548560 (1996-08-01), Stephens, Jr. et al.
patent: 5559752 (1996-09-01), Stephens, Jr. et al.
patent: 5983314 (1999-11-01), Merritt
patent: 5991226 (1999-11-01), Bhullar
patent: 5991227 (1999-11-01), Park

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