Synchronous semiconductor memory device for reducing power...

Details Synchronous semiconductor memory device for reducing power... Synchronous semiconductor memory device for reducing power...

2006-10-30

2008-09-23

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189120, C365S203000

Reexamination Certificate

active

07428183

ABSTRACT:
A semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state that all banks are precharged; a delay locked loop (DLL) for synchronizing an internal clock with an external clock; and a DLL drive controller for controlling the delay locked loop in response to an idle state detection signal outputted from the idle state detector and a delay locked signal outputted from the DLL.

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