Synchronous semiconductor memory device capable of reducing powe

Details Synchronous semiconductor memory device capable of reducing powe Synchronous semiconductor memory device capable of reducing powe

1999-03-23

2000-04-25

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365299, 36523003, G11C 800

Patent

active

060552069

ABSTRACT:
In a synchronous semiconductor memory device of the present invention, a main word driver and a sub decode driver have a function to take in a row decode signal in response to activation of a bank and to maintain the state of the row decode signal. Accordingly, of the circuits associated with row selection, a row pre-decoder, a row decoder and a row system control circuit can operate under a hierarchical power supply structure.

REFERENCES:
patent: 5384740 (1995-01-01), Etoh et al.
patent: 5606265 (1997-02-01), Sakata et al.
patent: 5640359 (1997-06-01), Suzuki et al.
patent: 5875149 (1999-02-01), Oh et al.
patent: 5959927 (1999-09-01), Yamagata et al.
"Ultra LSI Memory", K. Ito, pp. 356-366.
"Development of 18 Mbit Concurrent RDRAM", T. Ishikawa et al., NEC Giho, vol. 51, No. 3/1998, pp. 21-24.
"A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte/s Bandwidth", J. Yoo et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1635-1643.

Affiliated with

Also associated with

Rating

Synchronous semiconductor memory device capable of reducing powe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous semiconductor memory device capable of reducing powe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous semiconductor memory device capable of reducing powe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-999077