Synchronous semiconductor memory device capable of more reliable

Details Synchronous semiconductor memory device capable of more reliable Synchronous semiconductor memory device capable of more reliable

1999-06-03

2000-11-14

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365191, 365241, G11C 800

Patent

active

061479276

ABSTRACT:
In an SDRAM, an unlocked-state detection circuit detects whether synchronization between an external clock signal and an internal clock signal generated in the SDRAM according to the external clock signal is locked. When the internal clock signal is inappropriately locked, a signal output from the SDRAM to a memory controller transitions low, and the controller ignores data received and the SDRAM performs a process to ignore an input command.

REFERENCES:
patent: 5339440 (1994-08-01), Jacobs et al.
patent: 5629897 (1997-05-01), Iwamoto et al.
patent: 5708611 (1998-01-01), Iwamoto et al.
patent: 5754838 (1998-05-01), Shibata et al.
"A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", I. Young et al., IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
"Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and .+-.50 ps Jitter", I. Novof et al., IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp.1259-1266.

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