Synchronous semiconductor memory device capable of improving loa

Details Synchronous semiconductor memory device capable of improving loa Synchronous semiconductor memory device capable of improving loa

1998-01-16

1999-03-09

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523006, G11C 800

Patent

active

058810196

ABSTRACT:
In a synchronous semiconductor memory device including a memory cell array, a burst counter for generating an internal address signal in synchronization with an external clock signal and a decoder for reading out data from the memory cell array according to the internal address signal, an internal clock generation circuit generates an internal clock signal having a frequency equal to 1/2 of the frequency of the external clock signal in synchronization with the external clock signal, and a data output circuit outputs the data read out of the memory cell array in synchronization with both a rising edge and a falling edge of the internal clock signal.

REFERENCES:
patent: 5579267 (1996-11-01), Koshikawa
patent: 5691955 (1997-11-01), Yamauchi
patent: 5740121 (1998-04-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Synchronous semiconductor memory device capable of improving loa does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous semiconductor memory device capable of improving loa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous semiconductor memory device capable of improving loa will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1328201