Synchronous semiconductor memory device capable for more...

Details Synchronous semiconductor memory device capable for more... Synchronous semiconductor memory device capable for more...

2000-08-31

2002-03-26

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S226000

Reexamination Certificate

active

06363030

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to synchronous semiconductor memory devices operating in synchronization with an external clock signal.
More specifically, the present invention relates to improving the reliability of a memory system configured of a synchronous semiconductor memory device provided with a synchronizing internal clock generating circuit.
2. Description of the Background Art
With the improvement of microprocessors (MPUs) in operating speed in recent years, synchronous dynamic random access memory (SDRAM) and the like operating in synchronization with a clock signal have been used to achieve rapid access to dynamic random access memory (DRAM) and the like.
FIG. 30
is a timing chart for representing an operation of such an SDRAM in inputting data.
More specifically, in response to an external clock signal ext.CLK a delay locked loop (DLL) circuit mounted in the SDRAM generates a clock signal int.CLK of a data latch portion for externally receiving data.
In generating clock signal int.CLK, a clock signal input to the DLL circuit in the SDRAM delays by an internal delay &tgr;
1
, as compared to external clock signal ext.CLK.
There is also a delay time corresponding to a wiring delay (a time &tgr;
2
) cause before a signal output from the DLL circuit arrives at the data latch portion in a data input portion.
Thus the DLL circuit generates an internal clock signal which previously advances by time &tgr;
2
in phase with respect to a rising edge of external clock signal ext.CLK. In other words, the DLL circuit outputs a clock signal advancing by a time &tgr;
3
(=&tgr;
1
+&tgr;
2
) in phase as internal clock signal int.CLK.
Consequently, in a data input/output portion at the data latch portion, external and internal clock signals ext.CLK and int.CLK are signals matched in phase.
Thus, operation of the DLL circuit is calibrated so that a rising edge of external clock signal ext.CLK or a rising edge of internal clock signal int.CLK controlling the SDRAM's data receiving operation is positioned exactly at the center of an eye pattern of a data signal supplied to the SDRAM.
When a rising edge of internal clock signal ext.CLK is positioned at the center of the eye of data, operating margin will be maximized.
However, such improvement in operating margin can only be achieved when internal clock signal int.CLK is always generated reliably with respect to external clock signal ext.CLK.
Typically, however, system noise and the like often prevent the operation of generating internal clock signal int.CLK.
When system noise and the like prevent the phasing operation of the synchronizing internal clock generating circuit and locked phases of external and internal clock signals ext.CLK and int.CLK are unlocked, a data receiving margin can be degraded and a data-input error can be caused.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a synchronous semiconductor memory device free of data reception error when synchronous operation of a synchronizing internal clock generating circuit generating an internal clock signal is prevented by system noise or the like.
Another object of the present invention is to provide a synchronous semiconductor memory device provided with a synchronizing internal clock generating circuit capable of preventing a system error while reducing a time required for achieving synchronization with an external clock signal.
The present invention is a synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock signal and including a memory cell array, a control circuit, a synchronizing internal signal generating circuit, a synchronous condition detecting circuit and an output node.
The memory cell array has a plurality of memory cells arranged in rows and columns. The control circuit controls operation of the synchronous semiconductor memory device. The synchronizing internal signal generating circuit outputs an internal clock signal synchronized with an external clock signal.
The synchronous-condition detecting circuit monitors a condition of synchronization of the external and internal clock signals to generate a synchronous-condition determining signal. The output node outputs the synchronous-condition determining signal external to the synchronous semiconductor memory device.
Preferably the synchronous semiconductor memory device further includes a control signal input circuit synchronized with the internal clock signal to receive and supply a control signal to the control circuit and the control circuit halts a process associated with the control signal when the synchronous-condition determining signal indicates an inappropriate condition of synchronization.
Alternatively the synchronous semiconductor memory device preferably further includes a data input/output circuit holding and outputting data read from a memory cell selected in response to an address signal, and delaying outputting the read data in response to the synchronous-condition determining signal indicating an inappropriate condition of synchronization.
Thus a main advantage of the present invention is that a result of monitoring a condition of synchronization of external and internal clock signals that can be externally output allows a controller to detect an influence of system noise with the present invention incorporated in a memory system.
Another advantage of the present invention is that data communication stops when the internal clock signal is inappropriately locked, so that system error can be avoided when the inappropriately locked state is caused.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


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“A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors” by I. Young et al., IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
“Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Ranges and ±50 ps Jitter” by Novof et al., IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1259-1266.

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