Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-07-10
2004-07-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230060, C365S220000, C365S221000, C365S189011, C365S189040
Reexamination Certificate
active
06762972
ABSTRACT:
This application claims benefit and priority of Korean Patent Application No. 2001-43549, filed on Jul. 19, 2001, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device having a 4-bit pre-fetch mode and a method of processing data thereof.
2. Description of Related Art
A synchronous semiconductor memory device has widely been used as a main memory in various industrial fields such as a desk-top computer system or a portable computer system. Such synchronous semiconductor memory devices include single data rate synchronous semiconductor memory devices and double data rate synchronous semiconductor memory devices.
The single data rate synchronous semiconductor memory device receives a datum at a rising edge of a clock signal. The double data rate synchronous semiconductor memory device receives two data at the rising edge and falling edge of a clock signal.
The double data rate synchronous semiconductor memory device includes a memory cell array having an even-number memory cell array and an odd-number memory cell array, and sequentially receives two data in one clock cycle during a write operation before writing corresponding data concurrently in the even-number memory cell array and the odd-number memory cell array. For this reason, the double data rate synchronous semiconductor memory device is called a semiconductor memory device having a 2-bit pre-fetch mode. Accordingly, compared to the single data rate semiconductor memory device, the double data rate synchronous semiconductor memory device has an advantage in that data can be input or output at higher speed.
However, in a system requiring very high-speed operation, even the double data rate semiconductor memory device cannot operate at a high enough speed.
Recently, a synchronous semiconductor memory device having a 4-bit pre-fetch mode has been developed. The synchronous semiconductor memory device having a 4-bit pre-fetch mode includes four kinds of memory cell arrays, and sequentially receives four data at the rising edge and falling edge of a clock signal.
Operation of the synchronous semiconductor memory device having a 4-bit pre-fetch mode wherein a burst length is 4 follows: a row address is decoded to select a common word line of four memory cell arrays, and a partial column address (except a lower 2-bit column address) is decoded to select corresponding bit line pairs of the four memory cell arrays. When four data are sequentially input at a rising edge and a falling edge of a clock signal, the four serial data are converted into four parallel data, and the four parallel data are input into the corresponding memory cell arrays in accordance with the lower 2-bit column address.
However, the conventional synchronous semiconductor memory device having a 4-bit pre-fetch mode has a problem in that its circuit configuration is complicated.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a synchronous semiconductor memory device having a 4-bit pre-fetch mode and a method of processing data thereof but with a simplified circuit configuration.
In order to achieve the above object, the preferred embodiments of the present invention provide a synchronous semiconductor memory device having a 4-bit pre-fetch mode, comprising: first to fourth memory cell arrays each having memory cells, the memory cells being accessed concurrently in response to a signal generated by decoding a plurality of row addresses and a partial bit column address (except a 2-bit column address); a serial-parallel converting means converting a plurality of 4-bit data serially applied during a write operation into a plurality of 4-bit parallel data; a data loation control means location-controlling and outputting each of the plurality of the 4-bit parallel data output from the serial-parallel converting means in response to first to fourth decoding signals generated by decoding the 2-bit column address to the first to fourth memory cell arrays (by a sequential method or by an interleaving method) during the write operation; a sense amplifier amplifying a plurality of 4-bit data output from each of the first to fourth memory cell arrays and location-controlling and outputting them in response the first to fourth decoding signals (by a sequential method or by an interleaving method) during a read operation; and a parallel-serial converting means converting and outputting a plurality of 4-bit parallel data output from the sense amplifier during a read operation into a plurality of 4-bit serial data.
The data location control means includes a first switching means outputting the 4-bit data “as is” in response to the first decoding signal; a second switching means outputting first and third data among the 4-bit data to the second and fourth memory cell arrays, respectively, in response to the second decoding signal and outputting second and fourth data among the 4-bit data to the third and first memory cell arrays, respectively (in response to the second decoding signal in case of the sequential method and in response to the fourth decoding signal in case of the interleaving method); a third switching means outputting the first, the third, the second, and the fourth data among the 4-bit data to the third, the first, the fourth, and the second memory cell arrays in response to the third decoding signal, respectively; and a fourth switching means outputting first and third data among the 4-bit data to the fourth and second memory cell arrays, respectively, in response to the fourth decoding signal and outputting second and fourth data among the 4-bit data to the first and third memory cell arrays, respectively, in response to the fourth decoding signal (in case of the sequential method and in response to the second decoding signal in case of the interleaving method).
Each of the first to fourth switching means includes a CMOS transmission gate.
The sense amplifier includes a first sense amplifying means amplifying bit data output from the first to fourth memory cell arrays to output a first, a second, a third, and a fourth output data in response to the first decoding signal; a second sense amplifying means amplifying bit data output from the first and third memory cell arrays to output the fourth and second output data, respectively (in response to the second decoding signal in case of the sequential method and in response to the fourth decoding signal in case of the interleaving method) and amplifying bit data output from the second and fourth memory cell arrays to output the first and third output data, respectively, in response to the second decoding signal; a third sense amplifying means amplifying bit data output from the first to fourth memory cell arrays to output the third, the fourth, the first, and the second output data in response to the first decoding signal; and a fourth sense amplifying means amplifying bit data output from the first and third memory cell arrays to output the second and fourth output data, respectively (in response to the fourth decoding signal in case of the sequential method and in response to the second decoding signal in case of the interleaving method) and amplifying bit data output from the second and fourth memory cell arrays to output the third and first output data, respectively, in response to the fourth decoding signal.
Each of the first to fourth sense amplifying means includes an amplifying circuit for amplifying data output from the corresponding memory cell array; a latch for latching data output from the amplifying circuit in response to the corresponding decoding signal during the read operation; and a driver for driving data output from the latch.
Also, another preferred example of the present invention provides a synchronous semiconductor memory device having a 4-bit pre-fetch mode, comprising: first to fourth memory cell arrays
Marger & Johnson & McCollom, P.C.
Nelms David
Tran Long
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