Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

2006-10-20

2008-03-18

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S236000

Reexamination Certificate

active

07345950

ABSTRACT:
A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

REFERENCES:
patent: 6628276 (2003-09-01), Elliott
patent: 6643215 (2003-11-01), Kwak
patent: 6778465 (2004-08-01), Shin
patent: 6819626 (2004-11-01), Okuda et al.
patent: 6965530 (2005-11-01), Shimbayashi
patent: 7239574 (2007-07-01), Koji
patent: 2002-230973 (2002-08-01), None

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