Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

2008-09-02

2008-09-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

11609865

ABSTRACT:
Provided is a synchronous semiconductor memory device with improved latency control. In one embodiment, the synchronous semiconductor memory device may include a clock synchronizing circuit, a latency circuit, and a latency control circuit. The clock synchronizing circuit may receive an external clock signal and output a data output clock signal. The latency circuit may store a read signal in response to at least one sampling clock signal, generate a plurality of clock control signals in a sequential manner, generate a plurality of transfer clock signals synchronized with the plurality of clock control signals, and supply a latency signal in response to the transfer clock signals. The latency control circuit may delay the plurality of clock control signals by the sum of output delay time and the read command delay time so as to generate a plurality of sampling clock signals synchronized with the plurality of delayed clock control signals.

REFERENCES:
patent: 6687185 (2004-02-01), Keeth et al.
patent: 7012850 (2006-03-01), Demone
patent: 7065003 (2006-06-01), Lee et al.
patent: 7292500 (2007-11-01), Liu et al.
patent: 2005/0270852 (2005-12-01), Dietrich et al.
patent: 11-203859 (1999-07-01), None
patent: 2000-0045402 (2000-07-01), None
English language abstract for Korean Publication No. 2000-0045402.
English language abstract for Japanese Publication No. 11-203859.

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