Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1995-10-25

1997-01-07

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36518901, G11C 700

Patent

active

055924344

ABSTRACT:
To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.

REFERENCES:
patent: 5471430 (1995-11-01), Sawada et al.
patent: 5517462 (1996-05-01), Iwamoto et al.
"250 Mbyte/sec Synchronous DRAM Using a 3-State-Pipelined Architecture" Takai et al., '93 Symp. on VLSI circuit pp. 59-60.
"16 Mbit Synchronous DRAM with 125 Mbyte/sec Data Rate" Choi et al., 93 Symp. on VLSI circuit pp. 65-66.
"A 150-MHz-4-Bank 64 M-bit SDRAM with Address Incrementing Pipeline Scheme" Kodama et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers pp. 81-82.

Affiliated with

Also associated with

Rating

Synchronous semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1770502