Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1998-08-07

1999-11-30

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, 365204, 365203, G11C 800, G11C 700

Patent

active

059954388

ABSTRACT:
A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

REFERENCES:
patent: 4845677 (1989-07-01), Chappell et al.
patent: 5339274 (1994-08-01), Dhong et al.
patent: 5528552 (1996-06-01), Kamisaki
patent: 5594696 (1997-01-01), Komarak et al.
patent: 5825710 (1998-10-01), Jeng et al.

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