Synchronous semiconductor memory capable of saving a latency wit

Static information storage and retrieval – Addressing – Sync/clocking

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36518905, G11C 800

Patent

active

056871341

ABSTRACT:
In a synchronous semiconductor memory having a memory section (MS) for memorizing a particular datum, a single output latch circuit (32) is connected to an output side of the memory section and controlled by the use of a pulse signal whether or not the particular datum is passed through the output latch circuit. The pulse signal is produced in a pulse generator (31) to synchronize with an internal clock signal which is produced in an internal clock signal producing arrangement (21 and 22). The pulse signal has a pulse width which is independent of the internal clock signal and determined dependent on a timing when the memory section outputs the particular datum.

REFERENCES:
patent: 5083296 (1992-01-01), Hara
patent: 5341341 (1994-08-01), Fukuzo
patent: 5566108 (1996-10-01), Kitamura
patent: 5579267 (1996-11-01), Koshikawa

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