Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2001-07-16
2002-02-26
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S233100, C365S195000, C365S193000, C365S191000, C365S189080, C365S189110, C365S189050, C365S189070
Reexamination Certificate
active
06351432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory apparatus comprising a latch circuit for latching an output of an input circuit that receives input information.
In particular, the present invention relates to a synchronous semiconductor memory apparatus comprising a latch circuit capable of reducing current consumption and an input information latch control method thereof.
2. Description of Related Art
In recent years, in a semiconductor storage apparatus, with improvement in processing capability of a personal computer or the like, there has been a strong demand for high speed data access, and a synchronous semiconductor memory apparatus for data input/output in synchronism with an external clock has been significantly advanced and developed. At the same time, there has been remarkable improvement in technique for hand held device. In a semiconductor storage apparatus as well, lower current consumption is expected. In a typical product field, a hand held device having its high level computing capability such as mobile personal computer (PC) or notebook type personal computer (PC) has been significantly developed. As a semiconductor storage apparatus to be mounted on such device, a synchronous semiconductor memory apparatus are required which are capable of achieving an operation for low current compensation represented by a synchronous dynamic random access memory. Approaches for low current consumption includes a variety of measures described later, including control that has been achieved in a system inactive state such as power-down mode.
FIG. 1
is a circuit block diagram depicting an input buffer circuit that receives a signal from an external pin. A variety of control signals (Control) such as /CS,/RAS,/CAS,/WE or the like, bank address BankAdd or address Add, and data DQ or write mask signal DQM and the like are input to the external pin, and a level converter circuit (Level Converter) (refer to
FIG. 15
) detects whether a voltage level of an input signal is high or low comparing with a predetermined reference voltage Vrf. Then, this voltage level is converted into an amplification level of an internal circuit. This circuit is provided in a differential amplifier circuit system as shown in
FIG. 15
, and can be composed of a CMOS logic circuit or the like. The level converted input signal is level converted by means of a level converter circuit (Level Converter), and is latched by means of a latch circuit (Latch) (refer to
FIG. 16
) in synchronism with a rising edge of an internal synchronous clock (int. CLK) in which driving capability is improved by means of a driver circuit (Driver), thereby determining setup and hold specifications for a signal utilized for an internal circuit (Int. Circuit) and applied to an external pin.
Here, let us take an example of a 64 megabit synchronous semiconductor memory apparatus. A set of address Add is composed of 14 bits including 1 bit of bank address BankAdd, and a set of data DQ is composed of 32 DQs. With further high capacity and an increased number of DQs, the number of input buffer circuits represented by a set of address BankAdd, Add, and a set of data DQ is prone to increase.
FIG. 2
is a diagram showing operating waveforms. In synchronism with a rising edge of an internal synchronous signal int. CLK that is a signal in the same phase as a synchronous signal CLK, all latch circuits (Latch) performs latch operation, thereby performing a latch operation of the bank address BankAdd and row addresses in an active command (ACTV) cycle in FIG.
2
. In
FIG. 2
, latch operation is performed in each cycle. In a current state in which a plenty of pins are provided, low current consumption in an input buffer circuit is an important factor, and a variety of measures are discussed and taken.
For example, in Japanese Laid-open Patent Publication No. 11-273341 that is the first prior art, in a clock synchronous semiconductor apparatus, as shown in
FIG. 3
, an input buffer
100
is composed of: a differential input buffer
101
; a latch circuit
102
for latching a differential input buffer output; and a control circuit
103
for activating the differential input buffer
101
and the latch circuit
102
only at a predetermined timing.
That is, in the control circuit
103
, when both of the power-down signal PD and latch signal QCLKB are inactive (low level), the differential input buffer
101
and the latch circuit
102
are activated. Then, a voltage level of an external input signal IN compared with a reference voltage Vref is differentially amplified at a differential input buffer
101
, and is level converted as an output signal. Thereafter, a data holding operation is performed at the latch circuit
102
. When at least one of the power-down signal PD and latch signal QCLKB is active (high level), an output NOR
101
of the control circuit
103
turns OFF an NMOS transistor Q
106
. A signal obtained by inverting the output NOR
101
by means of an inverter IV turns OFF a PMOS transistor Q
105
, and turns OFF a clocked inverter CIV that configures the latch circuit
102
. Thus, a bias current of the differential input buffer
101
and a through current when data is switched in the latch circuit
102
do not flow altogether.
Therefore, in a normal operating state in which the power-down signal PD is inactive (low level), a latch signal QCLKB is inactive (low level) for a predetermined time in synchronism with a synchronous signal (clock) by which data is input, and is active (high level) in the subsequent latch period, whereby current consumption in an input data latch state is reduced.
In addition, in Japanese Laid-open Patent Publication No. 7-177015 that is the second prior art, in a synchronous semiconductor apparatus configuring two banks A and B, as shown in
FIG. 4
, when burst reading is performed in a bank selection state, the supply of a bias current to an input circuit at an initial stage is stopped.
That is, in the case where either one of the bank selection signals (signal ARAE for bank A and signal BRAE for bank B) enters a high level, and is selected (OR logic gate
201
); a burst read signal READB enters a high level and a burst read state (OR logic gate
202
); and a power-down signal PWDNB enters a low level, and is in a normal operating state, an output signal PWDNB
2
obtained by inverting a logical product (NAND logic gate
203
) of these signals (by an inverter
204
) enters a high level. This output signal PWDNB
2
is inverted by means of an inverter
205
, and bias PMOS transistors
206
and
207
of an input circuit at an initial stage are turned OFF, thereby stopping the supply of a bias current to the input circuit at the initial stage.
In addition, the timing chart in the figure denotes a 4-bit burst read in bank A. Prior to cycle T
1
, when /RAS is set at a low level, and a bank A active command is recognized at a rising edge of a synchronous clock CLK at cycle T
1
, a bank A selection signal ARAE goes to a high level in cycle T
1
. Next, in cycle T
1
, /RAS goes to a high level, and /CAS goes to a low level. In cycle T
2
, a bank A read command is recognized. In cycle T
2
, a burst read signal READB goes to a low level. At this time, assuming that an output enable mask signal OEMSK maintains a low level, a signal PWDNB
2
goes to a low level. In the subsequent cycle as well, a burst read operation is performed while a low level is maintained (T
3
to T
6
).
Therefore, after a burst bank A selection signal ARAE goes to a high level in cycle T
1
, a signal PWDNB
2
maintains a low level excluding a startup period of a burst read operation until the burst read signal READB goes to a low level in the subsequent cycle T
2
. Then, the power of an input circuit at the initial stage is cut in order to reduce current consumption.
Although a bank A burst read operation has been described above, of course, the similar operation is made for bank B.
In Japanese Laid-open Patent Publication No. 11-273341 that is the first prior art, the activatio
Higashiho Mitsuhiro
Ito Shigemasa
Arent Fox Kintner & Plotkin & Kahn, PLLC
Tran Andrew Q.
LandOfFree
Synchronous semiconductor memory apparatus and input... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronous semiconductor memory apparatus and input..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous semiconductor memory apparatus and input... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2941887