Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-09-16
2001-02-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230080, C365S189050
Reexamination Certificate
active
06188639
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a synchronous semiconductor memory, and more particularly to a synchronous semiconductor memory that includes first-stage input circuits for receiving external signals having reduced power consumption.
BACKGROUND OF THE INVENTION
Among the various types of memory devices are dynamic random access memories (DRAMs). A DRAM is typically a random access memory (RAM) that requires a refresh operation. One type of DRAM that can have an accelerated operation is a synchronous DRAM (SDRAM). A SDRAM can operate in synchronism with an external clock, and can have various operational values that can be set in synchronism with an external clock. Such operational values can include a column address strobe (CAS) latency, a burst length, and a wrap type.
A burst length can indicate the number of addresses that can be sequentially accessed with an initial address value. A wrap type can indicate a particular order in which addresses are accessed in a burst operation.
A CAS latency can indicate the number of clock cycles between the application of a command and the availability of data. Referring now to
FIG. 6
, a timing diagram is set forth illustrating the relationship between a clock signal CLK and a CAS latency.
FIG. 6
illustrates an example of a CAS latency of “2.” A command (such as a read command) is applied with an address (such as a column address). Due to the CAS latency value of 2, the corresponding data will be output two cycles after the command and address are entered.
Referring now to
FIG. 7
, a SDRAM is set forth in a block diagram. The SDRAM is disclosed in Japanese Patent Application Laid-Open No. 9-167485 (“Synchronous Semiconductor Memory Device”). As shown in
FIG. 7
, the SDRAM is designated by the general reference character
700
and includes a control buffer circuit
702
and a data mask (DQM) buffer circuit
704
. A control buffer circuit
702
can receive external control signals, including a row address strobe signal (/RAS), a column address strobe signal (/CAS), and a write enable signal (/WE). Such external control signals can be input in synchronism with an external clock signal (CLK). The DQM buffer circuit
704
can receive a mask enable signal (DQM) that can mask output read data in synchronism with the clock signal CLK. The DQM signal can also mask input write data. The output of the DQM buffer circuit
704
is an internal mask enable signal (QM).
The SDRAM
700
can further include a command decoder
706
and a read enable (RE) generating circuit
708
. The command decoder
706
can decode the output of control buffer circuit
702
and generate a read command (a read operation trigger signal R). A read command can initiate a data readout operation. The RE generating circuit
708
can receive a read command and count a number of clock cycle periods equal to a designated burst length. A read enable signal OEMF can be activated and de-activated according to the burst length count.
As further shown in
FIG. 7
, an output control circuit
710
can receive the read enable signal OEMF and the internal mask enable signal QM, and provide a data output enable signal (OEM). However, the read enable signal OEMF can also be input to a select circuit
712
of the read enable generating circuit
708
. The select circuit
712
can provide the read enable signal OEMF as an output when the CAS latency value is 1, otherwise it can output a logic high (power supply VDD) voltage.
Accordingly, the SDRAM
700
of
FIG. 7
can generate a data output enable (OEM) that can be activated or inactivated with the same timing as a clock signal CLK. This can prevent non-masked valid data from being erroneously masked, or masked valid data from not being masked due to erroneous SDRAM operation.
Furthermore, in the SDRAM
700
the data (DQ) pins and the input pins of the control buffer circuit
702
are separate, which can result in reduced power consumption in the first stage circuits associated with these pins. For example, when row address strobe (RAS) circuits are inactive (such as during precharge standby), CAS circuits are not activated, and thus the DQ signal can be inactive. In addition, there may be other modes where the RAS circuits may be activated, while the CAS circuits remain inactive (such as an auto refresh operation or a CAS-before-RAS “CBR” refresh). In such modes, the DQ signal can be inactive.
Referring now to
FIG. 8
, another example of a SDRAM is illustrated. The SDRAM is disclosed in Patent Publication No. 2605576 (Japanese Patent Application Laid-Open No. 6-290583, “Synchronous Semiconductor Memory”).
FIG. 8
shows a clock control circuit
800
for a SDRAM that can receive a clock signal CLK and a clock enable signal CKE, and generate a main signal &phgr;5. The main signal &phgr;5 can be a one-shot signal that is the main signal within the SDRAM. The pulse width of the main signal &phgr;5 is not dependent upon the width of the low and/or high portions of the clock signal CLK.
In
FIG. 8
, the clock enable signal CKE can control whether or not the main signal &phgr;5 is generated.
The SDRAM clock control circuit
800
is shown to include one first stage circuit
802
that can generate a control signal &phgr;1 from the clock signal CLK and another first stage circuit
804
that can generate an internal clock enable signal &phgr;2 from the clock enable signal CKE. The clock control circuit
800
further includes a first control circuit
806
, second control circuit
808
, and third control circuit
810
. The first control circuit
806
includes a first one-shot signal generating circuit
812
that can receive the control signal &phgr;1 and generate a timing signal &phgr;3 for the second control circuit
808
, and a second one-shot signal generating circuit
814
that can receive the control signal &phgr;1 and generate main signal &phgr;5. The second one-shot signal generating circuit
814
can be enabled or disabled by a clock control output signal &phgr;4 generated by the second control circuit
808
.
The second control circuit
808
receives the internal clock enable signal &phgr;2, and shifts it through a D-type flip-flop
816
and a D-type latch circuit
818
according to the timing signal &phgr;3.
The third control circuit
810
can receive the outputs of the D-type flip-flop
816
, a Dtype latch circuit
818
, and first stage circuit
804
, and generate the third control output &phgr;7.
The clock control circuit
800
can provide proper operation, even when a CAS latency value is as low as one.
Due to improvements in setup times, hold times and cycle times for the conventional SDRAM, the clock control circuit
800
can further provide current savings in the first control circuit
806
, that have typically been found only in asynchronous semiconductor memories. Such current savings can be accomplished by deactivating the second one-shot signal generating circuit
814
one clock cycle following a transition in the clock enable signal CKE.
While the above-described conventional SDRAM approach can provide some reductions in current consumption, such approaches provide no reduction in the amount of current consumed by a first stage circuit that receives a clock signal (such as first stage circuit
802
). Such further improvements in current reduction are desirable, as lower power SDRAMs are in greater demand due to the prevalence of portable equipment that utilizes such devices.
It would thus be desirable further reduce the power consumption of a high speed SDRAM.
SUMMARY OF THE INVENTION
The present invention may address the above mentioned problems, and can include a synchronous dynamic random access memory (SDRAM) having a first-stage control circuit that can generate a first stage control signal based on a clock signal, a clock enable signal, and a column address enable signal CASE. The SDRAM can further include a data input/output (DQ) first-stage control circuit coupled to a first-stage DQ circuit, and a data input/output mask (DQM) first-stage control circuit coupled to a first-stage DQM circuit. The
NEC Corporation
Nelms David
Walker Darryl G.
Yoha Connie C.
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