Synchronous semiconductor device allowing reduction in chip area

Details Synchronous semiconductor device allowing reduction in chip area Synchronous semiconductor device allowing reduction in chip area

1999-01-06

2000-04-18

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

36523003, G11C 800

Patent

active

06052331&

ABSTRACT:
A control signal generating circuit in a synchronous semiconductor memory device outputs timing signals for controlling activation of a word line and activation of sense amplifier, by delaying an external control signal by prescribed time periods. A bank control signal generating circuit provided for each bank holds activation of the timing signal from the control signal generating circuit, and outputs a signal for controlling timing of activation of the word line and timing of activation of the sense amplifier of the corresponding bank.

REFERENCES:
patent: 5483497 (1996-01-01), Mochizuki et al.
patent: 5592433 (1997-01-01), Tomita et al.
patent: 5592434 (1997-01-01), Iwamoto et al.
patent: 5764590 (1998-06-01), Iwamoto et al.
patent: 5844859 (1998-12-01), Iwamoto et al.
patent: 5867446 (1999-02-01), Konishi et al.

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