Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-10-02
1997-12-02
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Sync/clocking
365194, 326 96, G11C 700
Patent
active
056943717
ABSTRACT:
A synchronous semiconductor device includes an asynchronous circuit receiving a sequence of data signals supplied in synchronous with a first clock signal and outputting a sequence of resultant data signals based on the sequence of data signals, an output circuit clock generating circuit for generating second and third clock signals having phases inverse to each other from the first clock signal, and an output synchronizing circuit for outputting the sequence of resultant data signals in synchronous with the first clock signal using the second and third clock signals. The output circuit clock generating circuit includes a frequency dividing circuit for dividing the first clock signal in frequency such that the second and third clock signals have a frequency twice of that of the first clock signal and phases inverse to each other. In this case, the output synchronizing circuit includes a first latching section for latching a first resultant data signals of the sequence in response to the second clock signal, a second latching section for latching a second resultant data signals of the sequence in response to the third clock signal, the sequence of resultant data signals being composed of the first resultant data signals and the second resultant data signals which are different from the first resultant data signals, and a selecting section for alternately selecting the resultant data signals from the first and second latching sections for every time interval corresponding to one period of the first clock signal in accordance with the second and third clock signals. The output circuit clock generating circuit further includes a delay circuit for delaying the first clock signal by a time interval corresponding to an operation time of the asynchronous circuit to supply the delayed first clock signal to the frequency dividing circuit. Also, the output synchronizing circuit further includes a delay circuit for delaying the second and third clock signals to be supplied to the selecting section by an operation time of the first and second latching sections.
REFERENCES:
patent: 4658253 (1987-04-01), Johnson
patent: 5124589 (1992-06-01), Shiomi et al.
patent: 5384737 (1995-01-01), Childs et al.
patent: 5444667 (1995-08-01), Obara
NEC Corporation
Nguyen Tan T.
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