Television – Synchronization – Sync separation
Reexamination Certificate
2000-09-28
2003-05-13
Lee, Michael H. (Department: 2614)
Television
Synchronization
Sync separation
C348S547000
Reexamination Certificate
active
06563545
ABSTRACT:
TECHNICAL FIELD
The present invention relates to synchronous processor circuits in a color receiver and, more specifically, to a synchronous processor circuit for reproducing a synchronizing signal externally provided by a video signal source to a color receiver, and supplying the synchronizing signal to each circuit block in the color receiver.
BACKGROUND ART
FIG. 14
is a block diagram showing the structure of a conventional synchronous processor circuit. In
FIG. 14
, the synchronous processor circuit includes an LPF
1
to which a composite signal
5
is externally provided, and a vertical synchronization separating signal
6
is separated therefrom and outputted; a phase delay part
2
for receiving the composite signal
5
and outputting a plurality of horizontal synchronizing signals
19
to
24
each differently delayed in phase; and a vertical synchronizing signal reproduction circuit
3
for receiving the plurality of horizontal synchronizing signals
19
to
24
each differently delayed in phase and the vertical synchronization separating signal
6
and outputting a vertical synchronizing signal
8
. The phase delay part
2
includes first to sixth phase delay circuits
201
to
206
. The LPF is a low pass filter. The operation of this synchronous processor circuit is described next below.
FIG. 15
is a time chart which explains the operation of the conventional synchronous processor circuit. In the upper part of the drawing, t
1
to t
13
indicate time at a regular interval. To be specific, time t
1
to time t
13
indicate timing for a horizontal synchronizing signal to rise. As shown in
FIG. 15
, the composite signal
5
externally provided to a display is a synchronizing signal onto which a vertical synchronizing signal and a horizontal synchronizing signal are superimposed.
In
FIG. 15
, the horizontal synchronizing signal is a pulse signal which rises every time at times t
1
to time t
13
. The vertical synchronizing signal is a pulse signal which rises at time t
4
and falls at time t
8
. Once inputted into the LPF
1
, such composite signal
5
is cut off with any horizontal synchronizing frequency component which is high in frequency. Therefore, the LPF
1
is capable of reproducing the vertical synchronization separating signal
6
with any horizontal synchronizing frequency component subtracted from the composite signal
5
.
The composite signal
5
is also provided to each of the first to sixth phase delay circuits
201
to
206
in the phase delay part
2
. Those inputted composite signals
5
each generate a pulse corresponding to a period of the horizontal synchronizing signal. By using the pulses corresponding to the period of the horizontal synchronizing signal, the first to sixth phase delay circuits
201
to
206
output horizontal synchronizing signals
19
to
24
varied in phase with a predetermined interval in the corresponding phase delay circuit, respectively. The horizontal synchronizing signals
19
to
24
phase-delayed as such and the vertical synchronization separating signal
6
are provided to the vertical synchronizing signal reproduction circuit
3
. The vertical synchronizing signal reproduction circuit
3
outputs the vertical synchronizing signal
8
having the phase relationship with the horizontal synchronizing signal determined.
Next, the vertical synchronizing signal reproduction circuit
3
is described for its structure and operation in detail.
FIG. 16
is a diagram showing an exemplary detailed structure of the vertical synchronizing signal reproduction circuit
3
. In
FIG. 16
, the vertical synchronizing signal reproduction circuit
3
includes flip-flops
10
to
13
, each of which receives the phase-delayed horizontal synchronizing signal
19
,
21
,
22
, or
24
and the vertical synchronization separating signal
6
; a NAND gate
15
which receives signals from the flip-flops
10
and
11
; a NAND gate
16
which receives signals from the flip-flops
12
and
13
; a set-reset flip-flop
17
in which a signal from the NAND gate
15
goes to the set and a signal from the NAND gate
16
to the reset; a multiplexer
18
which receives a signal from the set-reset flip-flop
17
as a control signal and the phase-delayed horizontal synchronizing signals
20
and
23
, and outputs a signal
27
which is either one of the horizontal synchronizing signals; and a flip-flop
14
which receives the vertical synchronization separating signal
6
and the output signal
27
from the multiplexer
18
, and outputs the vertical synchronizing signal
8
.
In
FIG. 16
, the flip-flop
14
plays a a role as a latch means for latching a vertical synchronization separating signal, and outputting a synchronizing signal having the phase relationship with the horizontal synchronizing signal determined. The multiplexer
18
plays a role as a signal selection means for selecting, for output, a signal for latching the vertical synchronization separating signal from among a plurality of phase-delayed signals. The flip-flops
10
to
13
, the NAND gates
15
and
16
, and the set-reset flip-flop
17
play a role as signal selection control means for outputting a signal to control the multiplexer
18
which phase-delayed signal is selected therein. The operation of such structured vertical synchronizing signal reproduction circuit
3
is described next below by referring to
FIGS. 16 and 17
.
FIG. 17
is a time chart showing the operation of the vertical synchronizing signal reproduction circuit
3
from time t
4
to time t
5
in FIG.
15
. In
FIG. 17
, a timing (denoted by time tA in the drawing) which coincides with a threshold value between a high level and a low level of the vertical synchronization separating signal
6
is observed between timings for the phase-delayed synchronizing signals
19
and
21
to rise. In such case, as shown in
FIG. 17
, the output signal from the NAND gate
15
changes in level from high to low with the timing when the phase-delayed horizontal synchronizing signal
21
rises. The signal is a set incoming signal
25
which is inputted into the set terminal of the set-reset flip-flop
17
.
Further, in
FIG. 17
, the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal
6
is not observed between timings for the phase-delayed horizontal synchronizing signals
22
and
24
to rise. Therefore, as shown in
FIG. 17
, an output signal
26
from the NAND gate
16
remains in the high level. The signal is a reset incoming signal
26
which is inputted into the reset terminal of the set-reset flip-flop
17
.
Once such set incoming signal
25
and reset incoming signal
26
are provided to the set-reset flip-flop
17
, as shown in
FIG. 17
, an output signal
33
from the set-reset flip-flop
17
is fixed in the low level. The output signal
33
from the set-reset flip-flop
17
is provided to a control terminal of the multiplexer
18
.
When receiving a signal high in level in the control terminal, the multiplexer
18
selects the phase-delayed horizontal synchronizing signal
20
for output. When a signal low in level is inputted thereto, the multiplexer
18
selects the phase-delayed horizontal synchronizing signal
23
for output. Accordingly, the multiplexer
18
having the signal low in level provided to its control terminal selects and outputs the phase-delayed horizontal synchronizing signal
23
.
The phase-delayed horizontal synchronizing signal
23
can assuredly be latched with the vertical synchronization separating signal
6
with the timing which coincides with the threshold value between the high level and low level thereof. This is because, as described in the foregoing, the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal
6
is observed between the timings for the phase-delayed horizontal synchronizing signals
19
and
21
to rise. Therefore, it is not certain whether the phase-delayed horizontal synchronizing signal
20
between the
Lee Michael H.
Matsushita Electric - Industrial Co., Ltd.
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