Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1981-05-26
1983-12-13
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307243, 307510, 307481, 328109, 328116, 328152, 3408255, H03K 17693, H03K 1726, H03K 5153, H03K 522
Patent
active
044206950
ABSTRACT:
A logic circuit is connected to "n" input terminals having a descending order of priority 1, . . . k, . . . n, and to "n" corresponding output terminals for causing a logical "true" signal to be provided from any given output terminal in response to a logical "true" signal being provided at its corresponding input terminal when a logical "true" signal is not provided at any higher priority input terminal. The logic circuit includes "n" logic elements, each of which is connected between one of the input terminals and its corresponding output terminal and each of which has an enable input and an enable output, wherein the logic elements are interconnected with the enable input of the "kth" logic element being connected to the enable output of the "(k-1)th" logic element. Each logic element is adapted for providing a logical "true" signal to the output terminal connected thereto only in response to both a logical "true" signal at the corresponding input terminal and an enable signal at its enable input, and is further adapted for providing an enable signal at its enable output only if a "true" signal is provided to its enable input, and it does not provide a logical "true" signal to the output terminal connected to the logic element. The current path between the enable input and the enable output in each logic element includes a FET connected in series between the enable input and the enable output, with its gate being coupled to the corresponding input terminal for preventing an enabling signal from being provided from the enable output when a logical "true" signal is provided at the corresponding input terminal. An inhibit circuit responds to an inhibit signal by inhibiting the provision of an enabling signal to the enable input of the first logic element.
REFERENCES:
patent: 2794121 (1957-05-01), Bjornson
patent: 3199081 (1965-08-01), Kok et al.
patent: 3573487 (1971-04-01), Polkinghorn
patent: 3898618 (1975-08-01), Scheuneman
Leventhal, Introduction to Microprocessors: Software, Hardware, Programming, Prentice-Hall, Inc. (Pub), Englewood Cliffs, N.J., 1978, pp. 442-445, 478, 479, 482-484.
Anagnos Larry N.
Bertelson David R.
National Semiconductor Corporation
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