Synchronous power down clock oscillator device

Details Synchronous power down clock oscillator device Synchronous power down clock oscillator device

1995-09-22

1996-10-22

Mis, David

Oscillators

Combined with particular output coupling network

331173, 331175, 327142, 327161, 327544, H03B 506, H03K 3012, H03K 3014, H03L 300

Patent

active

055681000

ABSTRACT:
This invention provides a synchronous, power down oscillating device that provides only uniform pulses having no glitches at its output. The circuit is able to provide a synchronous output for two low power stand-by modes of a battery powered device. The circuit includes an oscillator that sends an oscillator signal to a synchronizing chain of D flip-flops. Input to the flip-flops is provided through an OR gate. The output of the flip-flops is logically ORed with the oscillator signal. The resultant output from the circuit is always a synchronized signal.

REFERENCES:
patent: 3947697 (1976-03-01), Archer et al.
patent: 4641044 (1987-02-01), Shiraishi
patent: 4864255 (1989-09-01), Yoshida
patent: 5225723 (1993-07-01), Drako et al.
patent: 5369311 (1994-11-01), Wang et al.
patent: 5440250 (1995-08-01), Albert

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