Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1998-09-04
2001-02-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S291000
Reexamination Certificate
active
06188262
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to clock systems for control of computers or other electronic circuits, and in particular to a distributed clock system for providing signals corresponding to phases of a master clock.
In the manufacture of computer systems and other circuits, clock signals are often provided to various elements such as components or circuits, on a single chip, or to elements scattered throughout the computer system itself. For a complex network of data communication paths, such as found in a conventional computer system, whether distributed on a single chip or over several chips, many clock signals must occur at times precisely related to the clock signals of adjacent parts of the system. In such a system, “adjacent” can mean parts of the circuit which are disposed relatively far away from one another but are adjacent in an electronic timing sense. As computer systems have evolved to operate at higher and higher clock speeds, the design and debugging of such clock distribution systems has become an extraordinarily difficult task.
In typical prior art computer systems, a master clock signal is generated for, or otherwise supplied to, a chip or printed circuit board. The clock signal is then distributed using conductive lines throughout the circuit. The designer of such a system must take great care to ensure that the clock signal arrives at an appropriate time at each of the circuits it controls. This is time consuming and expensive.
Typical prior art clock distribution systems are described in: Bakoglu, H. B.,
Circuits, Interconnections, and Packaging for VLSI
, Addison-Wesley (1990); Glasser, Lance A., et al.,
The Design and Analysis of VLSI Circuits
, Addison-Wesley (1985); Rettberg, Randall D., et al., U.S. Pat. No. 4,700,347, entitled “Digital Phase Adjustment” (Oct. 1985); Eby Friedman, “Clock Distribution,” IEEE Press ( ); and Weste & Eschraghian,
Principles of CMOS VLSI Design,
2
nd edition, Addison-Wesley (1993).
SUMMARY OF THE INVENTION
The techniques described below provide synchronous clock signals in as many phases as the designer of a given datapath circuit finds useful. We term such a system a “polyphase” clock distribution system because it produces as many clock phases as are necessary. The polyphase clock distribution system explicitly recognizes timing constraints of the datapath control so that each clock phase meets the specific needs of the local data circuits that use it. All clock signals are synchronous with the global clock signal, but each clock signal acquires a phase appropriate to local conditions.
An embodiment of a polyphase clock distribution system consists of a network of simple circuits embodying the timing constraints of the computer or other circuit being controlled on the chip. Wherever there is a path on the chip for data to pass from one register to another, a corresponding segment of the polyphase clock distribution network provides clock signals for both sender and receiver. Each segment of the polyphase clock distribution network ensures the compatibility of the clock signals for its particular sender and its particular receiver. The receiver's clock signal lags that of the sender by enough time to permit data to flow, but by no more than necessary. The next clock signal at the sender follows the previous clock signal at the receiver by an interval long enough to avoid data ambiguity.
A complex chip has many datapaths, and its polyphase clock distribution system must have correspondingly many segments. These segments of the polyphase clock distribution system generally exhibit the same topology that appears in the datapaths on the chip. Where several datapaths on the chip meet, the corresponding segments of the polyphase clock distribution system will also meet. Generally there is a one-to-one correspondence between junctions of the datapaths and junctions of the segments of the polyphase clock distribution system.
At each junction of datapaths a register or latch serves as sender or receiver for the data paths coming into and leaving that junction. The clock for the register or latch at the junction must be compatible with the needs of all the datapaths in which that junction register appears. The circuits in the corresponding junction of timing segments of the polyphase clock distribution system ensure that compatibility.
The polyphase clock distribution system ensures compatibility at each junction by delaying each clock event until all constraints on it have been met. For example, consider a register that takes data from several sources. The junction circuits of the polyphase clock distribution system time-position the clock signal that captures data into such a register late enough to ensure that all incoming data are available at the moment of capture, and time-position the clock signal to retain data until the data have reached all intended destinations.
If no external timing signal is provided, a polyphase clock distribution system will oscillate at the maximum frequency compatible with the timing constraints it embodies. For example, if the slowest datapath in the network requires X nanoseconds between its sending and receiving clocks, and Y nanoseconds between its receiving clock and the next sending clock, such a system can produce clock signals only every X+Y nanoseconds. Moreover, if these are the slowest constraints for the complete system, the entire polyphase clock distribution network will oscillate with a period of X+Y nanoseconds. The period of self-oscillation of the polyphase clock distribution system for a complex network is the shortest period compatible with all of the constraints it embodies. The system goes as fast as the constraints permit.
If a periodic timing signal with period longer than the self-oscillation period of the polyphase clock distribution system is injected into a polyphase clock distribution system, the polyphase system will everywhere adopt that period. The intended use of the polyphase clock distribution system is to distribute such a periodic signal throughout the chip. Each local clock signal will exhibit the same period and the same frequency, but each will have a unique phase determined by local need.
The polyphase clock system provides numerous advantages over conventional clock distribution systems. For example, the polyphase clock distribution system controls clock skew in a local, rather than global, manner, thus simplifying the task of designing clock circuits. Moreover, the phase of local clocks matches the needs of local circuits. The global clock signals operate at lower power levels, acquiring higher power only locally where broad data paths require large drivers. The polyphase clock system makes “time borrowing,” in which one stage of a pipeline “borrows” some time from another stage, relatively easy. Additionally, the phase of the local clock signals retains a proper phase relationship over a wide range of clock frequencies, including very low clock frequencies appropriate for reducing power consumption in certain modes of operation. As will be evident from the description below, the polyphase clock system enables modifications to the design of the datapath without requiring complete revision of the clock distribution system. Furthermore, electrical current demands are distributed more uniformly over the clock cycle than they are when a conventional clock is used. These advantages are discussed in more detail below.
In one embodiment of the polyphase clock distribution system, clock signals are provided in a plurality of phases to an associated circuit. In its simplest form, the system includes a plurality of clock signal generators coupled together in series, with each clock signal generator providing a first control signal to the subsequent clock signal generator in the series to permit that clock signal generator to switch from a first state to a second state, and each subsequent clock signal generator provides a second control signal to the predecessor clock signal generator in the series to permit that clock signal
Lam Tuan T.
Nguyen Linh
Sun Microsystems Inc.
Townsend and Townsend / and Crew LLP
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